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Merge pull request #3808 from ReinUsesLisp/wait-for-idle
{maxwell_3d,buffer_cache}: Implement memory barriers using 3D registers
This commit is contained in:
commit
2aff0b4733
@ -88,10 +88,6 @@ public:
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map->MarkAsWritten(true);
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MarkRegionAsWritten(map->GetStart(), map->GetEnd() - 1);
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}
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} else {
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if (map->IsWritten()) {
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WriteBarrier();
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}
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}
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return {ToHandle(block), static_cast<u64>(block->GetOffset(cpu_addr))};
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@ -253,8 +249,6 @@ protected:
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virtual BufferType ToHandle(const OwnerBuffer& storage) = 0;
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virtual void WriteBarrier() = 0;
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virtual OwnerBuffer CreateBlock(VAddr cpu_addr, std::size_t size) = 0;
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virtual void UploadBlockData(const OwnerBuffer& buffer, std::size_t offset, std::size_t size,
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@ -184,6 +184,10 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
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}
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switch (method) {
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case MAXWELL3D_REG_INDEX(wait_for_idle): {
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rasterizer.WaitForIdle();
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break;
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}
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case MAXWELL3D_REG_INDEX(shadow_ram_control): {
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shadow_state.shadow_ram_control = static_cast<Regs::ShadowRamControl>(method_call.argument);
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break;
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@ -709,7 +709,9 @@ public:
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union {
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struct {
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INSERT_UNION_PADDING_WORDS(0x45);
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INSERT_UNION_PADDING_WORDS(0x44);
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u32 wait_for_idle;
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struct {
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u32 upload_address;
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@ -1536,6 +1538,7 @@ private:
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static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(wait_for_idle, 0x44);
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ASSERT_REG_POSITION(macros, 0x45);
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ASSERT_REG_POSITION(shadow_ram_control, 0x49);
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ASSERT_REG_POSITION(upload, 0x60);
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@ -80,6 +80,9 @@ public:
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/// and invalidated
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virtual void FlushAndInvalidateRegion(VAddr addr, u64 size) = 0;
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/// Notify the host renderer to wait for previous primitive and compute operations.
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virtual void WaitForIdle() = 0;
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/// Notify the rasterizer to send all written commands to the host GPU.
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virtual void FlushCommands() = 0;
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@ -51,10 +51,6 @@ Buffer OGLBufferCache::CreateBlock(VAddr cpu_addr, std::size_t size) {
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return std::make_shared<CachedBufferBlock>(cpu_addr, size);
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}
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void OGLBufferCache::WriteBarrier() {
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glMemoryBarrier(GL_SHADER_STORAGE_BARRIER_BIT);
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}
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GLuint OGLBufferCache::ToHandle(const Buffer& buffer) {
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return buffer->GetHandle();
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}
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@ -59,8 +59,6 @@ protected:
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GLuint ToHandle(const Buffer& buffer) override;
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void WriteBarrier() override;
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void UploadBlockData(const Buffer& buffer, std::size_t offset, std::size_t size,
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const u8* data) override;
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@ -746,6 +746,17 @@ void RasterizerOpenGL::FlushAndInvalidateRegion(VAddr addr, u64 size) {
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InvalidateRegion(addr, size);
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}
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void RasterizerOpenGL::WaitForIdle() {
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// Place a barrier on everything that is not framebuffer related.
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// This is related to another flag that is not currently implemented.
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glMemoryBarrier(GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT | GL_ELEMENT_ARRAY_BARRIER_BIT |
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GL_UNIFORM_BARRIER_BIT | GL_TEXTURE_FETCH_BARRIER_BIT |
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GL_SHADER_IMAGE_ACCESS_BARRIER_BIT | GL_COMMAND_BARRIER_BIT |
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GL_PIXEL_BUFFER_BARRIER_BIT | GL_TEXTURE_UPDATE_BARRIER_BIT |
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GL_BUFFER_UPDATE_BARRIER_BIT | GL_TRANSFORM_FEEDBACK_BARRIER_BIT |
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GL_SHADER_STORAGE_BARRIER_BIT | GL_QUERY_BUFFER_BARRIER_BIT);
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}
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void RasterizerOpenGL::FlushCommands() {
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// Only flush when we have commands queued to OpenGL.
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if (num_queued_commands == 0) {
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@ -75,6 +75,7 @@ public:
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void SignalSyncPoint(u32 value) override;
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void ReleaseFences() override;
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void FlushAndInvalidateRegion(VAddr addr, u64 size) override;
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void WaitForIdle() override;
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void FlushCommands() override;
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void TickFrame() override;
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bool AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Regs::Surface& src,
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@ -52,8 +52,6 @@ public:
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protected:
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VkBuffer ToHandle(const Buffer& buffer) override;
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void WriteBarrier() override {}
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Buffer CreateBlock(VAddr cpu_addr, std::size_t size) override;
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void UploadBlockData(const Buffer& buffer, std::size_t offset, std::size_t size,
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@ -299,7 +299,7 @@ RasterizerVulkan::RasterizerVulkan(Core::System& system, Core::Frontend::EmuWind
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buffer_cache(*this, system, device, memory_manager, scheduler, staging_pool),
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sampler_cache(device),
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fence_manager(system, *this, device, scheduler, texture_cache, buffer_cache, query_cache),
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query_cache(system, *this, device, scheduler) {
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query_cache(system, *this, device, scheduler), wfi_event{device.GetLogical().CreateEvent()} {
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scheduler.SetQueryCache(query_cache);
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}
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@ -573,6 +573,26 @@ void RasterizerVulkan::FlushAndInvalidateRegion(VAddr addr, u64 size) {
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InvalidateRegion(addr, size);
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}
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void RasterizerVulkan::WaitForIdle() {
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// Everything but wait pixel operations. This intentionally includes FRAGMENT_SHADER_BIT because
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// fragment shaders can still write storage buffers.
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VkPipelineStageFlags flags =
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VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT | VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
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VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
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VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
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VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
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VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | VK_PIPELINE_STAGE_TRANSFER_BIT;
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if (device.IsExtTransformFeedbackSupported()) {
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flags |= VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT;
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}
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scheduler.RequestOutsideRenderPassOperationContext();
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scheduler.Record([event = *wfi_event, flags](vk::CommandBuffer cmdbuf) {
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cmdbuf.SetEvent(event, flags);
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cmdbuf.WaitEvents(event, flags, VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, {}, {}, {});
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});
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}
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void RasterizerVulkan::FlushCommands() {
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if (draw_counter > 0) {
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draw_counter = 0;
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@ -126,6 +126,7 @@ public:
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void SignalSyncPoint(u32 value) override;
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void ReleaseFences() override;
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void FlushAndInvalidateRegion(VAddr addr, u64 size) override;
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void WaitForIdle() override;
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void FlushCommands() override;
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void TickFrame() override;
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bool AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Regs::Surface& src,
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@ -275,6 +276,7 @@ private:
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vk::Buffer default_buffer;
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VKMemoryCommit default_buffer_commit;
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vk::Event wfi_event;
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std::array<View, Maxwell::NumRenderTargets> color_attachments;
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View zeta_attachment;
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@ -87,6 +87,7 @@ void Load(VkDevice device, DeviceDispatch& dld) noexcept {
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X(vkCmdSetStencilReference);
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X(vkCmdSetStencilWriteMask);
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X(vkCmdSetViewport);
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X(vkCmdWaitEvents);
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X(vkCreateBuffer);
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X(vkCreateBufferView);
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X(vkCreateCommandPool);
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@ -205,6 +205,7 @@ struct DeviceDispatch : public InstanceDispatch {
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PFN_vkCmdSetStencilReference vkCmdSetStencilReference;
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PFN_vkCmdSetStencilWriteMask vkCmdSetStencilWriteMask;
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PFN_vkCmdSetViewport vkCmdSetViewport;
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PFN_vkCmdWaitEvents vkCmdWaitEvents;
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PFN_vkCreateBuffer vkCreateBuffer;
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PFN_vkCreateBufferView vkCreateBufferView;
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PFN_vkCreateCommandPool vkCreateCommandPool;
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@ -958,6 +959,15 @@ public:
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dld->vkCmdSetEvent(handle, event, stage_flags);
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}
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void WaitEvents(Span<VkEvent> events, VkPipelineStageFlags src_stage_mask,
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VkPipelineStageFlags dst_stage_mask, Span<VkMemoryBarrier> memory_barriers,
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Span<VkBufferMemoryBarrier> buffer_barriers,
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Span<VkImageMemoryBarrier> image_barriers) const noexcept {
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dld->vkCmdWaitEvents(handle, events.size(), events.data(), src_stage_mask, dst_stage_mask,
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memory_barriers.size(), memory_barriers.data(), buffer_barriers.size(),
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buffer_barriers.data(), image_barriers.size(), image_barriers.data());
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}
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void BindTransformFeedbackBuffersEXT(u32 first, u32 count, const VkBuffer* buffers,
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const VkDeviceSize* offsets,
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const VkDeviceSize* sizes) const noexcept {
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