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Replace old FragmentHeader for the new Header
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parent
e926757c8f
commit
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@ -5,8 +5,8 @@
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#pragma once
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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namespace Tegra::Shader {
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@ -72,7 +72,7 @@ struct Header {
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INSERT_PADDING_BYTES(2); // OmapSystemValuesC
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INSERT_PADDING_BYTES(5); // OmapFixedFncTexture[10]
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INSERT_PADDING_BYTES(1); // OmapReserved
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} ps;
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} vtg;
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struct {
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INSERT_PADDING_BYTES(3); // ImapSystemValuesA
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@ -82,14 +82,20 @@ struct Header {
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INSERT_PADDING_BYTES(2); // ImapSystemValuesC
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INSERT_PADDING_BYTES(10); // ImapFixedFncTexture[10]
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INSERT_PADDING_BYTES(2); // ImapReserved
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INSERT_PADDING_BYTES(4); // OmapTarget[8]
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union {
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BitField<0, 1, u32> omap_sample_mask;
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BitField<1, 1, u32> omap_depth;
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BitField<2, 30, u32> omap_reserved;
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struct {
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u32 target;
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union {
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BitField<0, 1, u32> sample_mask;
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BitField<1, 1, u32> depth;
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BitField<2, 30, u32> reserved;
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};
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} omap;
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} vtg;
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} sph;
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bool IsColorComponentOutputEnabled(u32 render_target, u32 component) const {
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const u32 bit = render_target * 4 + component;
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return omap.target & (1 << bit);
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}
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} ps;
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};
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};
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static_assert(sizeof(Header) == 0x50, "Incorrect structure size");
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@ -689,23 +689,6 @@ public:
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}
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private:
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// Shader program header for a Fragment Shader.
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struct FragmentHeader {
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INSERT_PADDING_WORDS(5);
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INSERT_PADDING_WORDS(13);
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u32 enabled_color_outputs;
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union {
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BitField<0, 1, u32> writes_samplemask;
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BitField<1, 1, u32> writes_depth;
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};
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bool IsColorComponentOutputEnabled(u32 render_target, u32 component) const {
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const u32 bit = render_target * 4 + component;
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return enabled_color_outputs & (1 << bit);
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}
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};
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static_assert(sizeof(FragmentHeader) == PROGRAM_HEADER_SIZE, "FragmentHeader size is wrong");
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/// Gets the Subroutine object corresponding to the specified address.
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const Subroutine& GetSubroutine(u32 begin, u32 end) const {
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const auto iter = subroutines.find(Subroutine{begin, end, suffix});
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@ -1011,10 +994,8 @@ private:
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/// Writes the output values from a fragment shader to the corresponding GLSL output variables.
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void EmitFragmentOutputsWrite() {
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ASSERT(stage == Maxwell3D::Regs::ShaderStage::Fragment);
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FragmentHeader header;
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std::memcpy(&header, program_code.data(), PROGRAM_HEADER_SIZE);
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ASSERT_MSG(header.writes_samplemask == 0, "Samplemask write is unimplemented");
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ASSERT_MSG(header.ps.omap.sample_mask == 0, "Samplemask write is unimplemented");
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// Write the color outputs using the data in the shader registers, disabled
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// rendertargets/components are skipped in the register assignment.
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@ -1023,7 +1004,7 @@ private:
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++render_target) {
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// TODO(Subv): Figure out how dual-source blending is configured in the Switch.
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for (u32 component = 0; component < 4; ++component) {
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if (header.IsColorComponentOutputEnabled(render_target, component)) {
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if (header.ps.IsColorComponentOutputEnabled(render_target, component)) {
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shader.AddLine(fmt::format("FragColor{}[{}] = {};", render_target, component,
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regs.GetRegisterAsFloat(current_reg)));
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++current_reg;
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@ -1031,7 +1012,7 @@ private:
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}
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}
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if (header.writes_depth) {
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if (header.ps.omap.depth) {
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// The depth output is always 2 registers after the last color output, and current_reg
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// already contains one past the last color register.
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