mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-08-21 22:33:22 +02:00
shader_decode: Improve zero flag implementation
This commit is contained in:
parent
d911740e5d
commit
2d6c064e66
@ -45,8 +45,6 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF_MSG(
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instr.fmul.tab5c68_0 != 1, "FMUL tab5cb8_0({}) is not implemented",
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instr.fmul.tab5c68_0.Value()); // SMO typical sends 1 here which seems to be the default
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in FMUL is not implemented");
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op_b = GetOperandAbsNegFloat(op_b, false, instr.fmul.negate_b);
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@ -75,21 +73,20 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
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value = GetSaturatedFloat(value, instr.alu.saturate_d);
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::FADD_C:
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case OpCode::Id::FADD_R:
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case OpCode::Id::FADD_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in FADD is not implemented");
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op_a = GetOperandAbsNegFloat(op_a, instr.alu.abs_a, instr.alu.negate_a);
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op_b = GetOperandAbsNegFloat(op_b, instr.alu.abs_b, instr.alu.negate_b);
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Node value = Operation(OperationCode::FAdd, PRECISE, op_a, op_b);
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value = GetSaturatedFloat(value, instr.alu.saturate_d);
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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@ -126,9 +123,6 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
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case OpCode::Id::FMNMX_C:
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case OpCode::Id::FMNMX_R:
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case OpCode::Id::FMNMX_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in FMNMX is not implemented");
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op_a = GetOperandAbsNegFloat(op_a, instr.alu.abs_a, instr.alu.negate_a);
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op_b = GetOperandAbsNegFloat(op_b, instr.alu.abs_b, instr.alu.negate_b);
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@ -136,9 +130,10 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
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const Node min = Operation(OperationCode::FMin, NO_PRECISE, op_a, op_b);
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const Node max = Operation(OperationCode::FMax, NO_PRECISE, op_a, op_b);
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const Node value = Operation(OperationCode::Select, NO_PRECISE, condition, min, max);
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SetRegister(bb, instr.gpr0,
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Operation(OperationCode::Select, NO_PRECISE, condition, min, max));
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::RRO_C:
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@ -22,24 +22,22 @@ u32 ShaderIR::DecodeArithmeticImmediate(BasicBlock& bb, u32 pc) {
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break;
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}
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case OpCode::Id::FMUL32_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.op_32.generates_cc,
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"Condition codes generation in FMUL32 is not implemented");
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Node value =
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Operation(OperationCode::FMul, PRECISE, GetRegister(instr.gpr8), GetImmediate32(instr));
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value = GetSaturatedFloat(value, instr.fmul32.saturate);
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SetInternalFlagsFromFloat(bb, value, instr.op_32.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::FADD32I: {
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UNIMPLEMENTED_IF_MSG(instr.op_32.generates_cc,
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"Condition codes generation in FADD32I is not implemented");
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const Node op_a = GetOperandAbsNegFloat(GetRegister(instr.gpr8), instr.fadd32i.abs_a,
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instr.fadd32i.negate_a);
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const Node op_b = GetOperandAbsNegFloat(GetImmediate32(instr), instr.fadd32i.abs_b,
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instr.fadd32i.negate_b);
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const Node value = Operation(OperationCode::FAdd, PRECISE, op_a, op_b);
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SetInternalFlagsFromFloat(bb, value, instr.op_32.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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@ -34,22 +34,20 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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case OpCode::Id::IADD_C:
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case OpCode::Id::IADD_R:
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case OpCode::Id::IADD_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in IADD is not implemented");
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UNIMPLEMENTED_IF_MSG(instr.alu.saturate_d, "IADD saturation not implemented");
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op_a = GetOperandAbsNegInteger(op_a, false, instr.alu_integer.negate_a, true);
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op_b = GetOperandAbsNegInteger(op_b, false, instr.alu_integer.negate_b, true);
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SetRegister(bb, instr.gpr0, Operation(OperationCode::IAdd, PRECISE, op_a, op_b));
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const Node value = Operation(OperationCode::IAdd, PRECISE, op_a, op_b);
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SetInternalFlagsFromInteger(bb, value, instr.op_32.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::IADD3_C:
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case OpCode::Id::IADD3_R:
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case OpCode::Id::IADD3_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in IADD3 is not implemented");
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Node op_c = GetRegister(instr.gpr39);
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const auto ApplyHeight = [&](IAdd3Height height, Node value) {
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@ -100,6 +98,7 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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return Operation(OperationCode::IAdd, NO_PRECISE, shifted, op_c);
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}();
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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@ -115,6 +114,8 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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const Node shift = Immediate(static_cast<u32>(instr.alu_integer.shift_amount));
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const Node shifted_a = Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, op_a, shift);
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const Node value = Operation(OperationCode::IAdd, NO_PRECISE, shifted_a, op_b);
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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@ -139,24 +140,19 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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case OpCode::Id::LOP_C:
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case OpCode::Id::LOP_R:
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case OpCode::Id::LOP_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in LOP is not implemented");
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if (instr.alu.lop.invert_a)
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op_a = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_a);
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if (instr.alu.lop.invert_b)
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op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b);
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WriteLogicOperation(bb, instr.gpr0, instr.alu.lop.operation, op_a, op_b,
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instr.alu.lop.pred_result_mode, instr.alu.lop.pred48);
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instr.alu.lop.pred_result_mode, instr.alu.lop.pred48,
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instr.generates_cc);
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break;
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}
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case OpCode::Id::LOP3_C:
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case OpCode::Id::LOP3_R:
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case OpCode::Id::LOP3_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in LOP3 is not implemented");
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const Node op_c = GetRegister(instr.gpr39);
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const Node lut = [&]() {
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if (opcode->get().GetId() == OpCode::Id::LOP3_R) {
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@ -166,15 +162,13 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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}
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}();
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WriteLop3Instruction(bb, instr.gpr0, op_a, op_b, op_c, lut);
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WriteLop3Instruction(bb, instr.gpr0, op_a, op_b, op_c, lut, instr.generates_cc);
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break;
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}
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case OpCode::Id::IMNMX_C:
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case OpCode::Id::IMNMX_R:
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case OpCode::Id::IMNMX_IMM: {
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UNIMPLEMENTED_IF(instr.imnmx.exchange != Tegra::Shader::IMinMaxExchange::None);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in IMNMX is not implemented");
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const bool is_signed = instr.imnmx.is_signed;
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@ -182,6 +176,8 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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const Node min = SignedOperation(OperationCode::IMin, is_signed, NO_PRECISE, op_a, op_b);
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const Node max = SignedOperation(OperationCode::IMax, is_signed, NO_PRECISE, op_a, op_b);
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const Node value = Operation(OperationCode::Select, NO_PRECISE, condition, min, max);
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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@ -247,7 +243,7 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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}
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void ShaderIR::WriteLop3Instruction(BasicBlock& bb, Register dest, Node op_a, Node op_b, Node op_c,
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Node imm_lut) {
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Node imm_lut, bool sets_cc) {
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constexpr u32 lop_iterations = 32;
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const Node one = Immediate(1);
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const Node two = Immediate(2);
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@ -284,6 +280,7 @@ void ShaderIR::WriteLop3Instruction(BasicBlock& bb, Register dest, Node op_a, No
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}
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}
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SetInternalFlagsFromInteger(bb, value, sets_cc);
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SetRegister(bb, dest, value);
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}
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@ -25,20 +25,17 @@ u32 ShaderIR::DecodeArithmeticIntegerImmediate(BasicBlock& bb, u32 pc) {
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switch (opcode->get().GetId()) {
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case OpCode::Id::IADD32I: {
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UNIMPLEMENTED_IF_MSG(instr.op_32.generates_cc,
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"Condition codes generation in IADD32I is not implemented");
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UNIMPLEMENTED_IF_MSG(instr.iadd32i.saturate, "IADD32I saturation is not implemented");
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op_a = GetOperandAbsNegInteger(op_a, false, instr.iadd32i.negate_a, true);
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const Node value = Operation(OperationCode::IAdd, PRECISE, op_a, op_b);
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SetInternalFlagsFromInteger(bb, value, instr.op_32.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::LOP32I: {
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UNIMPLEMENTED_IF_MSG(instr.op_32.generates_cc,
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"Condition codes generation in LOP32I is not implemented");
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if (instr.alu.lop32i.invert_a)
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op_a = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_a);
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@ -46,8 +43,7 @@ u32 ShaderIR::DecodeArithmeticIntegerImmediate(BasicBlock& bb, u32 pc) {
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op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b);
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WriteLogicOperation(bb, instr.gpr0, instr.alu.lop32i.operation, op_a, op_b,
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Tegra::Shader::PredicateResultMode::None,
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Tegra::Shader::Pred::UnusedIndex);
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PredicateResultMode::None, Pred::UnusedIndex, instr.op_32.generates_cc);
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break;
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}
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default:
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@ -60,7 +56,7 @@ u32 ShaderIR::DecodeArithmeticIntegerImmediate(BasicBlock& bb, u32 pc) {
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void ShaderIR::WriteLogicOperation(BasicBlock& bb, Register dest, LogicOperation logic_op,
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Node op_a, Node op_b, PredicateResultMode predicate_mode,
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Pred predicate) {
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Pred predicate, bool sets_cc) {
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const Node result = [&]() {
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switch (logic_op) {
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case LogicOperation::And:
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@ -77,11 +73,9 @@ void ShaderIR::WriteLogicOperation(BasicBlock& bb, Register dest, LogicOperation
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}
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}();
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if (dest != Register::ZeroIndex) {
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SetRegister(bb, dest, result);
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}
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SetInternalFlagsFromInteger(bb, result, sets_cc);
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SetRegister(bb, dest, result);
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using Tegra::Shader::PredicateResultMode;
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// Write the predicate value depending on the predicate mode.
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switch (predicate_mode) {
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case PredicateResultMode::None:
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@ -35,6 +35,7 @@ u32 ShaderIR::DecodeBfe(BasicBlock& bb, u32 pc) {
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const Node outer_shift =
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Operation(OperationCode::ILogicalShiftRight, NO_PRECISE, inner_shift, outer_shift_imm);
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SetInternalFlagsFromInteger(bb, outer_shift, instr.generates_cc);
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SetRegister(bb, instr.gpr0, outer_shift);
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break;
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}
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@ -16,8 +16,6 @@ u32 ShaderIR::DecodeBfi(BasicBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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UNIMPLEMENTED_IF(instr.generates_cc);
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const auto [base, packed_shift] = [&]() -> std::tuple<Node, Node> {
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switch (opcode->get().GetId()) {
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case OpCode::Id::BFI_IMM_R:
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@ -33,6 +31,8 @@ u32 ShaderIR::DecodeBfi(BasicBlock& bb, u32 pc) {
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const Node value =
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Operation(OperationCode::UBitfieldInsert, PRECISE, base, insert, offset, bits);
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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return pc;
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@ -33,15 +33,8 @@ u32 ShaderIR::DecodeConversion(BasicBlock& bb, u32 pc) {
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value = SignedOperation(OperationCode::ICastUnsigned, output_signed, NO_PRECISE, value);
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}
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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if (instr.generates_cc) {
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const Node zero_condition =
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SignedOperation(OperationCode::LogicalIEqual, output_signed, value, Immediate(0));
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SetInternalFlag(bb, InternalFlag::Zero, zero_condition);
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LOG_WARNING(HW_GPU, "I2I Condition codes implementation is incomplete.");
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}
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break;
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}
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case OpCode::Id::I2F_R:
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@ -64,6 +57,7 @@ u32 ShaderIR::DecodeConversion(BasicBlock& bb, u32 pc) {
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value = SignedOperation(OperationCode::FCastInteger, input_signed, PRECISE, value);
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value = GetOperandAbsNegFloat(value, false, instr.conversion.negate_a);
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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@ -103,6 +97,7 @@ u32 ShaderIR::DecodeConversion(BasicBlock& bb, u32 pc) {
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}();
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value = GetSaturatedFloat(value, instr.alu.saturate_d);
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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@ -21,8 +21,6 @@ u32 ShaderIR::DecodeFfma(BasicBlock& bb, u32 pc) {
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instr.ffma.tab5980_0.Value()); // Seems to be 1 by default based on SMO
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UNIMPLEMENTED_IF_MSG(instr.ffma.tab5980_1 != 0, "FFMA tab5980_1({}) not implemented",
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instr.ffma.tab5980_1.Value());
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in FFMA is not implemented");
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const Node op_a = GetRegister(instr.gpr8);
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@ -52,6 +50,7 @@ u32 ShaderIR::DecodeFfma(BasicBlock& bb, u32 pc) {
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Node value = Operation(OperationCode::FFma, PRECISE, op_a, op_b, op_c);
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value = GetSaturatedFloat(value, instr.alu.saturate_d);
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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return pc;
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@ -45,13 +45,12 @@ u32 ShaderIR::DecodeFloatSet(BasicBlock& bb, u32 pc) {
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const Node value =
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Operation(OperationCode::Select, PRECISE, predicate, true_value, false_value);
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SetRegister(bb, instr.gpr0, value);
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if (instr.generates_cc) {
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const Node is_zero = Operation(OperationCode::LogicalFEqual, value, Immediate(0.0f));
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SetInternalFlag(bb, InternalFlag::Zero, is_zero);
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LOG_WARNING(HW_GPU, "FSET condition code is incomplete");
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if (instr.fset.bf) {
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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} else {
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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}
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SetRegister(bb, instr.gpr0, value);
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return pc;
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}
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@ -32,6 +32,12 @@ u32 ShaderIR::DecodePredicateSetRegister(BasicBlock& bb, u32 pc) {
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const Node false_value = instr.pset.bf ? Immediate(0.0f) : Immediate(0);
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const Node value =
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Operation(OperationCode::Select, PRECISE, predicate, true_value, false_value);
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if (instr.pset.bf) {
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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} else {
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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}
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SetRegister(bb, instr.gpr0, value);
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return pc;
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@ -31,22 +31,20 @@ u32 ShaderIR::DecodeShift(BasicBlock& bb, u32 pc) {
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case OpCode::Id::SHR_C:
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case OpCode::Id::SHR_R:
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case OpCode::Id::SHR_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in SHR is not implemented");
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const Node value = SignedOperation(OperationCode::IArithmeticShiftRight,
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instr.shift.is_signed, PRECISE, op_a, op_b);
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::SHL_C:
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case OpCode::Id::SHL_R:
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case OpCode::Id::SHL_IMM:
|
||||
UNIMPLEMENTED_IF_MSG(instr.generates_cc,
|
||||
"Condition codes generation in SHL is not implemented");
|
||||
SetRegister(bb, instr.gpr0,
|
||||
Operation(OperationCode::ILogicalShiftLeft, PRECISE, op_a, op_b));
|
||||
case OpCode::Id::SHL_IMM: {
|
||||
const Node value = Operation(OperationCode::ILogicalShiftLeft, PRECISE, op_a, op_b);
|
||||
SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
|
||||
SetRegister(bb, instr.gpr0, value);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
UNIMPLEMENTED_MSG("Unhandled shift instruction: {}", opcode->get().GetName());
|
||||
}
|
||||
|
@ -38,9 +38,6 @@ u32 ShaderIR::DecodeVideo(BasicBlock& bb, u32 pc) {
|
||||
|
||||
switch (opcode->get().GetId()) {
|
||||
case OpCode::Id::VMAD: {
|
||||
UNIMPLEMENTED_IF_MSG(instr.generates_cc,
|
||||
"Condition codes generation in VMAD is not implemented");
|
||||
|
||||
const bool result_signed = instr.video.signed_a == 1 || instr.video.signed_b == 1;
|
||||
const Node op_c = GetRegister(instr.gpr39);
|
||||
|
||||
@ -53,8 +50,8 @@ u32 ShaderIR::DecodeVideo(BasicBlock& bb, u32 pc) {
|
||||
SignedOperation(OperationCode::IArithmeticShiftRight, result_signed, value, shift);
|
||||
}
|
||||
|
||||
SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
|
||||
SetRegister(bb, instr.gpr0, value);
|
||||
|
||||
break;
|
||||
}
|
||||
case OpCode::Id::VSETP: {
|
||||
|
@ -86,6 +86,7 @@ u32 ShaderIR::DecodeXmad(BasicBlock& bb, u32 pc) {
|
||||
sum = Operation(OperationCode::IBitwiseOr, NO_PRECISE, a, b);
|
||||
}
|
||||
|
||||
SetInternalFlagsFromInteger(bb, sum, instr.generates_cc);
|
||||
SetRegister(bb, instr.gpr0, sum);
|
||||
|
||||
return pc;
|
||||
|
@ -7,6 +7,7 @@
|
||||
|
||||
#include "common/assert.h"
|
||||
#include "common/common_types.h"
|
||||
#include "common/logging/log.h"
|
||||
#include "video_core/engines/shader_bytecode.h"
|
||||
#include "video_core/shader/shader_ir.h"
|
||||
|
||||
@ -356,6 +357,24 @@ void ShaderIR::SetTemporal(BasicBlock& bb, u32 id, Node value) {
|
||||
SetRegister(bb, Register::ZeroIndex + 1 + id, value);
|
||||
}
|
||||
|
||||
void ShaderIR::SetInternalFlagsFromFloat(BasicBlock& bb, Node value, bool sets_cc) {
|
||||
if (!sets_cc) {
|
||||
return;
|
||||
}
|
||||
const Node zerop = Operation(OperationCode::LogicalFEqual, value, Immediate(0.0f));
|
||||
SetInternalFlag(bb, InternalFlag::Zero, zerop);
|
||||
LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete");
|
||||
}
|
||||
|
||||
void ShaderIR::SetInternalFlagsFromInteger(BasicBlock& bb, Node value, bool sets_cc) {
|
||||
if (!sets_cc) {
|
||||
return;
|
||||
}
|
||||
const Node zerop = Operation(OperationCode::LogicalIEqual, value, Immediate(0));
|
||||
SetInternalFlag(bb, InternalFlag::Zero, zerop);
|
||||
LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete");
|
||||
}
|
||||
|
||||
Node ShaderIR::BitfieldExtract(Node value, u32 offset, u32 bits) {
|
||||
return Operation(OperationCode::UBitfieldExtract, NO_PRECISE, value, Immediate(offset),
|
||||
Immediate(bits));
|
||||
|
@ -649,6 +649,11 @@ private:
|
||||
/// Sets a temporal. Internally it uses a post-RZ register
|
||||
void SetTemporal(BasicBlock& bb, u32 id, Node value);
|
||||
|
||||
/// Sets internal flags from a float
|
||||
void SetInternalFlagsFromFloat(BasicBlock& bb, Node value, bool sets_cc = true);
|
||||
/// Sets internal flags from an integer
|
||||
void SetInternalFlagsFromInteger(BasicBlock& bb, Node value, bool sets_cc = true);
|
||||
|
||||
/// Conditionally absolute/negated float. Absolute is applied first
|
||||
Node GetOperandAbsNegFloat(Node value, bool absolute, bool negate);
|
||||
/// Conditionally saturates a float
|
||||
@ -725,9 +730,9 @@ private:
|
||||
void WriteLogicOperation(BasicBlock& bb, Tegra::Shader::Register dest,
|
||||
Tegra::Shader::LogicOperation logic_op, Node op_a, Node op_b,
|
||||
Tegra::Shader::PredicateResultMode predicate_mode,
|
||||
Tegra::Shader::Pred predicate);
|
||||
Tegra::Shader::Pred predicate, bool sets_cc);
|
||||
void WriteLop3Instruction(BasicBlock& bb, Tegra::Shader::Register dest, Node op_a, Node op_b,
|
||||
Node op_c, Node imm_lut);
|
||||
Node op_c, Node imm_lut, bool sets_cc);
|
||||
|
||||
template <typename... T>
|
||||
Node Operation(OperationCode code, const T*... operands) {
|
||||
|
Loading…
Reference in New Issue
Block a user