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Merge pull request #512 from Subv/fset
GPU: Corrected the FSET and I2F instructions.
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commit
37fd4e6d9b
@ -245,9 +245,9 @@ union Instruction {
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BitField<44, 1, u64> abs_b;
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BitField<45, 2, PredOperation> op;
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BitField<48, 4, PredCondition> cond;
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BitField<52, 1, u64> bf;
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BitField<53, 1, u64> neg_b;
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BitField<54, 1, u64> abs_a;
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BitField<52, 1, u64> bf;
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BitField<55, 1, u64> ftz;
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BitField<56, 1, u64> neg_imm;
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} fset;
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@ -871,8 +871,7 @@ private:
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ASSERT_MSG(!instr.conversion.saturate_a, "Unimplemented");
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switch (opcode->GetId()) {
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case OpCode::Id::I2I_R:
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case OpCode::Id::I2F_R: {
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case OpCode::Id::I2I_R: {
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ASSERT_MSG(!instr.conversion.selector, "Unimplemented");
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std::string op_a =
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@ -885,6 +884,17 @@ private:
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regs.SetRegisterToInteger(instr.gpr0, instr.conversion.is_signed, 0, op_a, 1, 1);
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break;
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}
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case OpCode::Id::I2F_R: {
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std::string op_a =
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regs.GetRegisterAsInteger(instr.gpr20, 0, instr.conversion.is_signed);
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if (instr.conversion.abs_a) {
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op_a = "abs(" + op_a + ')';
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}
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a, 1, 1);
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break;
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}
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case OpCode::Id::F2F_R: {
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std::string op_a = regs.GetRegisterAsFloat(instr.gpr20);
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@ -1078,7 +1088,12 @@ private:
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std::string predicate = "(((" + op_a + ") " + comparator + " (" + op_b + ")) " +
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combiner + " (" + second_pred + "))";
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regs.SetRegisterToFloat(instr.gpr0, 0, predicate + " ? 1.0 : 0.0", 1, 1);
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if (instr.fset.bf) {
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regs.SetRegisterToFloat(instr.gpr0, 0, predicate + " ? 1.0 : 0.0", 1, 1);
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} else {
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regs.SetRegisterToInteger(instr.gpr0, false, 0, predicate + " ? 0xFFFFFFFF : 0", 1,
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1);
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}
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break;
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}
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default: {
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