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shader/half_set: Implement HSET2_IMM
Add HSET2_IMM. Due to the complexity of the encoding avoid using BitField unions and read the relevant bits from the code itself. This is less error prone.
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@ -661,6 +661,10 @@ union Instruction {
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constexpr Instruction(u64 value) : value{value} {}
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constexpr Instruction(u64 value) : value{value} {}
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constexpr Instruction(const Instruction& instr) : value(instr.value) {}
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constexpr Instruction(const Instruction& instr) : value(instr.value) {}
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constexpr bool Bit(u64 offset) const {
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return ((value >> offset) & 1) != 0;
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}
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BitField<0, 8, Register> gpr0;
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BitField<0, 8, Register> gpr0;
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BitField<8, 8, Register> gpr8;
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BitField<8, 8, Register> gpr8;
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union {
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union {
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@ -1874,7 +1878,9 @@ public:
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HSETP2_C,
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HSETP2_C,
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HSETP2_R,
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HSETP2_R,
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HSETP2_IMM,
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HSETP2_IMM,
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HSET2_C,
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HSET2_R,
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HSET2_R,
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HSET2_IMM,
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POPC_C,
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POPC_C,
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POPC_R,
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POPC_R,
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POPC_IMM,
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POPC_IMM,
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@ -2194,7 +2200,9 @@ private:
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INST("0111111-1-------", Id::HSETP2_C, Type::HalfSetPredicate, "HSETP2_C"),
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INST("0111111-1-------", Id::HSETP2_C, Type::HalfSetPredicate, "HSETP2_C"),
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INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP2_R"),
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INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP2_R"),
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INST("0111111-0-------", Id::HSETP2_IMM, Type::HalfSetPredicate, "HSETP2_IMM"),
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INST("0111111-0-------", Id::HSETP2_IMM, Type::HalfSetPredicate, "HSETP2_IMM"),
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INST("0111110-1-------", Id::HSET2_C, Type::HalfSet, "HSET2_C"),
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INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"),
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INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"),
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INST("0111110-0-------", Id::HSET2_IMM, Type::HalfSet, "HSET2_IMM"),
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INST("010110111010----", Id::FCMP_RR, Type::Arithmetic, "FCMP_RR"),
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INST("010110111010----", Id::FCMP_RR, Type::Arithmetic, "FCMP_RR"),
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INST("010010111010----", Id::FCMP_RC, Type::Arithmetic, "FCMP_RC"),
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INST("010010111010----", Id::FCMP_RC, Type::Arithmetic, "FCMP_RC"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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@ -13,55 +13,101 @@
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namespace VideoCommon::Shader {
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namespace VideoCommon::Shader {
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using std::move;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::PredCondition;
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u32 ShaderIR::DecodeHalfSet(NodeBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeHalfSet(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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const auto opcode = OpCode::Decode(instr);
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if (instr.hset2.ftz == 0) {
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PredCondition cond;
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bool bf;
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bool ftz;
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bool neg_a;
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bool abs_a;
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bool neg_b;
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bool abs_b;
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switch (opcode->get().GetId()) {
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case OpCode::Id::HSET2_C:
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case OpCode::Id::HSET2_IMM:
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cond = instr.hsetp2.cbuf_and_imm.cond;
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bf = instr.Bit(53);
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ftz = instr.Bit(54);
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neg_a = instr.Bit(43);
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abs_a = instr.Bit(44);
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neg_b = instr.Bit(56);
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abs_b = instr.Bit(54);
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break;
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case OpCode::Id::HSET2_R:
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cond = instr.hsetp2.reg.cond;
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bf = instr.Bit(49);
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ftz = instr.Bit(50);
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neg_a = instr.Bit(43);
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abs_a = instr.Bit(44);
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neg_b = instr.Bit(31);
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abs_b = instr.Bit(30);
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break;
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default:
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UNREACHABLE();
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}
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Node op_b = [this, instr, opcode] {
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switch (opcode->get().GetId()) {
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case OpCode::Id::HSET2_C:
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// Inform as unimplemented as this is not tested.
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UNIMPLEMENTED_MSG("HSET2_C is not implemented");
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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case OpCode::Id::HSET2_R:
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return GetRegister(instr.gpr20);
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case OpCode::Id::HSET2_IMM:
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return UnpackHalfImmediate(instr, true);
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default:
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UNREACHABLE();
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return Node{};
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}
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}();
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if (!ftz) {
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LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
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LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
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}
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}
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Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hset2.type_a);
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Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hset2.type_a);
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op_a = GetOperandAbsNegHalf(op_a, instr.hset2.abs_a, instr.hset2.negate_a);
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op_a = GetOperandAbsNegHalf(op_a, abs_a, neg_a);
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Node op_b = [&]() {
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switch (opcode->get().GetId()) {
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switch (opcode->get().GetId()) {
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case OpCode::Id::HSET2_R:
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case OpCode::Id::HSET2_R:
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return GetRegister(instr.gpr20);
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op_b = GetOperandAbsNegHalf(move(op_b), abs_b, neg_b);
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[[fallthrough]];
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case OpCode::Id::HSET2_C:
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op_b = UnpackHalfFloat(move(op_b), instr.hset2.type_b);
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break;
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default:
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default:
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UNREACHABLE();
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break;
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return Immediate(0);
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}
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}
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}();
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op_b = UnpackHalfFloat(op_b, instr.hset2.type_b);
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op_b = GetOperandAbsNegHalf(op_b, instr.hset2.abs_b, instr.hset2.negate_b);
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const Node second_pred = GetPredicate(instr.hset2.pred39, instr.hset2.neg_pred);
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Node second_pred = GetPredicate(instr.hset2.pred39, instr.hset2.neg_pred);
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const Node comparison_pair = GetPredicateComparisonHalf(instr.hset2.cond, op_a, op_b);
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Node comparison_pair = GetPredicateComparisonHalf(cond, op_a, op_b);
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const OperationCode combiner = GetPredicateCombiner(instr.hset2.op);
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const OperationCode combiner = GetPredicateCombiner(instr.hset2.op);
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// HSET2 operates on each half float in the pack.
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// HSET2 operates on each half float in the pack.
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std::array<Node, 2> values;
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std::array<Node, 2> values;
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for (u32 i = 0; i < 2; ++i) {
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for (u32 i = 0; i < 2; ++i) {
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const u32 raw_value = instr.hset2.bf ? 0x3c00 : 0xffff;
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const u32 raw_value = bf ? 0x3c00 : 0xffff;
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const Node true_value = Immediate(raw_value << (i * 16));
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Node true_value = Immediate(raw_value << (i * 16));
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const Node false_value = Immediate(0);
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Node false_value = Immediate(0);
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const Node comparison =
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Operation(OperationCode::LogicalPick2, comparison_pair, Immediate(i));
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const Node predicate = Operation(combiner, comparison, second_pred);
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Node comparison = Operation(OperationCode::LogicalPick2, comparison_pair, Immediate(i));
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Node predicate = Operation(combiner, comparison, second_pred);
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values[i] =
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values[i] =
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Operation(OperationCode::Select, NO_PRECISE, predicate, true_value, false_value);
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Operation(OperationCode::Select, predicate, move(true_value), move(false_value));
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}
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}
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const Node value = Operation(OperationCode::UBitwiseOr, NO_PRECISE, values[0], values[1]);
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Node value = Operation(OperationCode::UBitwiseOr, values[0], values[1]);
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SetRegister(bb, instr.gpr0, value);
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SetRegister(bb, instr.gpr0, move(value));
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return pc;
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return pc;
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}
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}
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