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shader/decode: Reduce severity of arithmetic rounding warnings
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c4374d0d41
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39c66abd91
@ -43,12 +43,12 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) {
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case OpCode::Id::FMUL_IMM: {
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// FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
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if (instr.fmul.tab5cb8_2 != 0) {
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LOG_WARNING(HW_GPU, "FMUL tab5cb8_2({}) is not implemented",
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instr.fmul.tab5cb8_2.Value());
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LOG_DEBUG(HW_GPU, "FMUL tab5cb8_2({}) is not implemented",
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instr.fmul.tab5cb8_2.Value());
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}
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if (instr.fmul.tab5c68_0 != 1) {
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LOG_WARNING(HW_GPU, "FMUL tab5cb8_0({}) is not implemented",
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instr.fmul.tab5c68_0.Value());
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LOG_DEBUG(HW_GPU, "FMUL tab5cb8_0({}) is not implemented",
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instr.fmul.tab5c68_0.Value());
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}
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op_b = GetOperandAbsNegFloat(op_b, false, instr.fmul.negate_b);
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@ -21,8 +21,8 @@ u32 ShaderIR::DecodeArithmeticHalf(NodeBlock& bb, u32 pc) {
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if (opcode->get().GetId() == OpCode::Id::HADD2_C ||
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opcode->get().GetId() == OpCode::Id::HADD2_R) {
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if (instr.alu_half.ftz != 0) {
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LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName());
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if (instr.alu_half.ftz == 0) {
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LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
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}
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}
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@ -19,12 +19,12 @@ u32 ShaderIR::DecodeArithmeticHalfImmediate(NodeBlock& bb, u32 pc) {
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const auto opcode = OpCode::Decode(instr);
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if (opcode->get().GetId() == OpCode::Id::HADD2_IMM) {
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if (instr.alu_half_imm.ftz != 0) {
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LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName());
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if (instr.alu_half_imm.ftz == 0) {
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LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
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}
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} else {
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if (instr.alu_half_imm.precision != Tegra::Shader::HalfPrecision::None) {
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LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName());
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if (instr.alu_half_imm.precision != Tegra::Shader::HalfPrecision::FTZ) {
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LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
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}
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}
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@ -19,10 +19,10 @@ u32 ShaderIR::DecodeFfma(NodeBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF_MSG(instr.ffma.cc != 0, "FFMA cc not implemented");
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if (instr.ffma.tab5980_0 != 1) {
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LOG_WARNING(HW_GPU, "FFMA tab5980_0({}) not implemented", instr.ffma.tab5980_0.Value());
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LOG_DEBUG(HW_GPU, "FFMA tab5980_0({}) not implemented", instr.ffma.tab5980_0.Value());
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}
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if (instr.ffma.tab5980_1 != 0) {
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LOG_WARNING(HW_GPU, "FFMA tab5980_1({}) not implemented", instr.ffma.tab5980_1.Value());
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LOG_DEBUG(HW_GPU, "FFMA tab5980_1({}) not implemented", instr.ffma.tab5980_1.Value());
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}
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const Node op_a = GetRegister(instr.gpr8);
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@ -20,8 +20,8 @@ u32 ShaderIR::DecodeHalfSet(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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if (instr.hset2.ftz != 0) {
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LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName());
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if (instr.hset2.ftz == 0) {
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LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
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}
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Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hset2.type_a);
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@ -19,7 +19,9 @@ u32 ShaderIR::DecodeHalfSetPredicate(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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LOG_DEBUG(HW_GPU, "ftz={}", static_cast<u32>(instr.hsetp2.ftz));
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if (instr.hsetp2.ftz != 0) {
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LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
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}
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Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hsetp2.type_a);
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op_a = GetOperandAbsNegHalf(op_a, instr.hsetp2.abs_a, instr.hsetp2.negate_a);
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