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shader_decode: Implement LOP32I
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@ -10,15 +10,81 @@
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namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::LogicOperation;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Pred;
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using Tegra::Shader::PredicateResultMode;
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using Tegra::Shader::Register;
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u32 ShaderIR::DecodeArithmeticIntegerImmediate(BasicBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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UNIMPLEMENTED();
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Node op_a = GetRegister(instr.gpr8);
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Node op_b = Immediate(static_cast<s32>(instr.alu.imm20_32));
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switch (opcode->get().GetId()) {
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case OpCode::Id::LOP32I: {
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UNIMPLEMENTED_IF_MSG(instr.op_32.generates_cc,
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"Condition codes generation in LOP32I is not implemented");
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if (instr.alu.lop32i.invert_a)
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op_a = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_a);
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if (instr.alu.lop32i.invert_b)
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op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b);
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WriteLogicOperation(bb, instr.gpr0, instr.alu.lop32i.operation, op_a, op_b,
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Tegra::Shader::PredicateResultMode::None,
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Tegra::Shader::Pred::UnusedIndex);
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled ArithmeticIntegerImmediate instruction: {}",
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opcode->get().GetName());
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}
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return pc;
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}
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void ShaderIR::WriteLogicOperation(BasicBlock& bb, Register dest, LogicOperation logic_op,
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Node op_a, Node op_b, PredicateResultMode predicate_mode,
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Pred predicate) {
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const Node result = [&]() {
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switch (logic_op) {
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case LogicOperation::And:
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return Operation(OperationCode::IBitwiseAnd, PRECISE, op_a, op_b);
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case LogicOperation::Or:
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return Operation(OperationCode::IBitwiseOr, PRECISE, op_a, op_b);
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case LogicOperation::Xor:
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return Operation(OperationCode::IBitwiseXor, PRECISE, op_a, op_b);
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case LogicOperation::PassB:
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return op_b;
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default:
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UNIMPLEMENTED_MSG("Unimplemented logic operation={}", static_cast<u32>(logic_op));
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}
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}();
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if (dest != Register::ZeroIndex) {
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SetRegister(bb, dest, result);
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}
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using Tegra::Shader::PredicateResultMode;
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// Write the predicate value depending on the predicate mode.
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switch (predicate_mode) {
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case PredicateResultMode::None:
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// Do nothing.
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return;
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case PredicateResultMode::NotZero: {
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// Set the predicate to true if the result is not zero.
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const Node compare = Operation(OperationCode::LogicalIEqual, result, Immediate(0));
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SetPredicate(bb, static_cast<u64>(predicate), compare);
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unimplemented predicate result mode: {}",
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static_cast<u32>(predicate_mode));
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}
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}
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} // namespace VideoCommon::Shader
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@ -697,6 +697,11 @@ private:
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Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
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bool is_array, std::size_t bias_offset, std::vector<Node>&& coords);
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void WriteLogicOperation(BasicBlock& bb, Tegra::Shader::Register dest,
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Tegra::Shader::LogicOperation logic_op, Node op_a, Node op_b,
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Tegra::Shader::PredicateResultMode predicate_mode,
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Tegra::Shader::Pred predicate);
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template <typename... T>
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inline Node Operation(OperationCode code, const T*... operands) {
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return StoreNode(OperationNode(code, operands...));
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