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kepler_compute: Implement texture queries
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2e5b5c2358
commit
3a450c1395
@ -2,6 +2,7 @@
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// Licensed under GPLv2 or any later version
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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// Refer to the license.txt file included.
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#include <bitset>
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#include "common/assert.h"
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "common/logging/log.h"
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#include "core/core.h"
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#include "core/core.h"
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@ -49,6 +50,33 @@ void KeplerCompute::CallMethod(const GPU::MethodCall& method_call) {
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}
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}
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}
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}
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Tegra::Texture::FullTextureInfo KeplerCompute::GetTexture(std::size_t offset) const {
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const std::bitset<8> cbuf_mask = launch_description.const_buffer_enable_mask.Value();
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ASSERT(cbuf_mask[regs.tex_cb_index]);
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const auto& texinfo = launch_description.const_buffer_config[regs.tex_cb_index];
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ASSERT(texinfo.Address() != 0);
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const GPUVAddr address = texinfo.Address() + offset * sizeof(Texture::TextureHandle);
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ASSERT(address < texinfo.Address() + texinfo.size);
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const Texture::TextureHandle tex_handle{memory_manager.Read<u32>(address)};
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return GetTextureInfo(tex_handle, offset);
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}
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Texture::FullTextureInfo KeplerCompute::GetTextureInfo(const Texture::TextureHandle tex_handle,
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std::size_t offset) const {
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return Texture::FullTextureInfo{static_cast<u32>(offset), GetTICEntry(tex_handle.tic_id),
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GetTSCEntry(tex_handle.tsc_id)};
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}
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u32 KeplerCompute::AccessConstBuffer32(u64 const_buffer, u64 offset) const {
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const auto& buffer = launch_description.const_buffer_config[const_buffer];
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u32 result;
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std::memcpy(&result, memory_manager.GetPointer(buffer.Address() + offset), sizeof(u32));
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return result;
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}
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void KeplerCompute::ProcessLaunch() {
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void KeplerCompute::ProcessLaunch() {
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const GPUVAddr launch_desc_loc = regs.launch_desc_loc.Address();
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const GPUVAddr launch_desc_loc = regs.launch_desc_loc.Address();
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memory_manager.ReadBlockUnsafe(launch_desc_loc, &launch_description,
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memory_manager.ReadBlockUnsafe(launch_desc_loc, &launch_description,
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@ -60,4 +88,29 @@ void KeplerCompute::ProcessLaunch() {
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rasterizer.DispatchCompute(code_addr);
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rasterizer.DispatchCompute(code_addr);
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}
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}
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Texture::TICEntry KeplerCompute::GetTICEntry(u32 tic_index) const {
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const GPUVAddr tic_address_gpu{regs.tic.Address() + tic_index * sizeof(Texture::TICEntry)};
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Texture::TICEntry tic_entry;
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memory_manager.ReadBlockUnsafe(tic_address_gpu, &tic_entry, sizeof(Texture::TICEntry));
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const auto r_type{tic_entry.r_type.Value()};
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const auto g_type{tic_entry.g_type.Value()};
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const auto b_type{tic_entry.b_type.Value()};
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const auto a_type{tic_entry.a_type.Value()};
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// TODO(Subv): Different data types for separate components are not supported
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DEBUG_ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
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return tic_entry;
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}
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Texture::TSCEntry KeplerCompute::GetTSCEntry(u32 tsc_index) const {
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const GPUVAddr tsc_address_gpu{regs.tsc.Address() + tsc_index * sizeof(Texture::TSCEntry)};
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Texture::TSCEntry tsc_entry;
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memory_manager.ReadBlockUnsafe(tsc_address_gpu, &tsc_entry, sizeof(Texture::TSCEntry));
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return tsc_entry;
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}
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} // namespace Tegra::Engines
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} // namespace Tegra::Engines
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@ -12,6 +12,7 @@
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "video_core/engines/engine_upload.h"
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#include "video_core/engines/engine_upload.h"
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#include "video_core/gpu.h"
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#include "video_core/gpu.h"
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#include "video_core/textures/texture.h"
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namespace Core {
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namespace Core {
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class System;
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class System;
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@ -111,7 +112,7 @@ public:
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INSERT_PADDING_WORDS(0x3FE);
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INSERT_PADDING_WORDS(0x3FE);
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u32 texture_const_buffer_index;
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u32 tex_cb_index;
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INSERT_PADDING_WORDS(0x374);
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INSERT_PADDING_WORDS(0x374);
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};
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};
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@ -149,7 +150,7 @@ public:
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union {
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union {
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BitField<0, 8, u32> const_buffer_enable_mask;
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BitField<0, 8, u32> const_buffer_enable_mask;
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BitField<29, 2, u32> cache_layout;
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BitField<29, 2, u32> cache_layout;
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} memory_config;
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};
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INSERT_PADDING_WORDS(0x8);
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INSERT_PADDING_WORDS(0x8);
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@ -194,6 +195,14 @@ public:
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/// Write the value to the register identified by method.
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/// Write the value to the register identified by method.
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void CallMethod(const GPU::MethodCall& method_call);
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void CallMethod(const GPU::MethodCall& method_call);
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Tegra::Texture::FullTextureInfo GetTexture(std::size_t offset) const;
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/// Given a Texture Handle, returns the TSC and TIC entries.
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Texture::FullTextureInfo GetTextureInfo(const Texture::TextureHandle tex_handle,
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std::size_t offset) const;
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u32 AccessConstBuffer32(u64 const_buffer, u64 offset) const;
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private:
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private:
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Core::System& system;
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Core::System& system;
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VideoCore::RasterizerInterface& rasterizer;
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VideoCore::RasterizerInterface& rasterizer;
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@ -201,6 +210,12 @@ private:
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Upload::State upload_state;
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Upload::State upload_state;
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void ProcessLaunch();
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void ProcessLaunch();
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/// Retrieves information about a specific TIC entry from the TIC buffer.
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Texture::TICEntry GetTICEntry(u32 tic_index) const;
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/// Retrieves information about a specific TSC entry from the TSC buffer.
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Texture::TSCEntry GetTSCEntry(u32 tsc_index) const;
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};
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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#define ASSERT_REG_POSITION(field_name, position) \
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@ -218,12 +233,12 @@ ASSERT_REG_POSITION(launch, 0xAF);
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ASSERT_REG_POSITION(tsc, 0x557);
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ASSERT_REG_POSITION(tsc, 0x557);
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ASSERT_REG_POSITION(tic, 0x55D);
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ASSERT_REG_POSITION(tic, 0x55D);
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ASSERT_REG_POSITION(code_loc, 0x582);
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ASSERT_REG_POSITION(code_loc, 0x582);
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ASSERT_REG_POSITION(texture_const_buffer_index, 0x982);
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ASSERT_REG_POSITION(tex_cb_index, 0x982);
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ASSERT_LAUNCH_PARAM_POSITION(program_start, 0x8);
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ASSERT_LAUNCH_PARAM_POSITION(program_start, 0x8);
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ASSERT_LAUNCH_PARAM_POSITION(grid_dim_x, 0xC);
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ASSERT_LAUNCH_PARAM_POSITION(grid_dim_x, 0xC);
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ASSERT_LAUNCH_PARAM_POSITION(shared_alloc, 0x11);
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ASSERT_LAUNCH_PARAM_POSITION(shared_alloc, 0x11);
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ASSERT_LAUNCH_PARAM_POSITION(block_dim_x, 0x12);
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ASSERT_LAUNCH_PARAM_POSITION(block_dim_x, 0x12);
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ASSERT_LAUNCH_PARAM_POSITION(memory_config, 0x14);
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ASSERT_LAUNCH_PARAM_POSITION(const_buffer_enable_mask, 0x14);
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ASSERT_LAUNCH_PARAM_POSITION(const_buffer_config, 0x1D);
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ASSERT_LAUNCH_PARAM_POSITION(const_buffer_config, 0x1D);
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#undef ASSERT_REG_POSITION
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#undef ASSERT_REG_POSITION
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@ -801,6 +801,8 @@ void RasterizerOpenGL::DispatchCompute(GPUVAddr code_addr) {
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}
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}
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auto kernel = shader_cache.GetComputeKernel(code_addr);
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auto kernel = shader_cache.GetComputeKernel(code_addr);
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SetupComputeImages(kernel);
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const auto [program, next_bindings] = kernel->GetProgramHandle({});
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const auto [program, next_bindings] = kernel->GetProgramHandle({});
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state.draw.shader_program = program;
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state.draw.shader_program = program;
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state.draw.program_pipeline = 0;
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state.draw.program_pipeline = 0;
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@ -922,7 +924,7 @@ void RasterizerOpenGL::SetupComputeConstBuffers(const Shader& kernel) {
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const auto& launch_desc = system.GPU().KeplerCompute().launch_description;
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const auto& launch_desc = system.GPU().KeplerCompute().launch_description;
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for (const auto& entry : kernel->GetShaderEntries().const_buffers) {
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for (const auto& entry : kernel->GetShaderEntries().const_buffers) {
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const auto& config = launch_desc.const_buffer_config[entry.GetIndex()];
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const auto& config = launch_desc.const_buffer_config[entry.GetIndex()];
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const std::bitset<8> mask = launch_desc.memory_config.const_buffer_enable_mask.Value();
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const std::bitset<8> mask = launch_desc.const_buffer_enable_mask.Value();
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Tegra::Engines::ConstBufferInfo buffer;
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Tegra::Engines::ConstBufferInfo buffer;
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buffer.address = config.Address();
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buffer.address = config.Address();
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buffer.size = config.size;
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buffer.size = config.size;
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@ -1038,6 +1040,24 @@ bool RasterizerOpenGL::SetupTexture(const Shader& shader, u32 binding,
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return false;
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return false;
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}
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}
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void RasterizerOpenGL::SetupComputeImages(const Shader& shader) {
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const auto& compute = system.GPU().KeplerCompute();
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const auto& entries = shader->GetShaderEntries().images;
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for (u32 bindpoint = 0; bindpoint < entries.size(); ++bindpoint) {
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const auto& entry = entries[bindpoint];
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const auto texture = [&]() {
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if (!entry.IsBindless()) {
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return compute.GetTexture(entry.GetOffset());
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}
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const auto cbuf = entry.GetBindlessCBuf();
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Tegra::Texture::TextureHandle tex_handle;
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tex_handle.raw = compute.AccessConstBuffer32(cbuf.first, cbuf.second);
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return compute.GetTextureInfo(tex_handle, entry.GetOffset());
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}();
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UNIMPLEMENTED();
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}
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}
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void RasterizerOpenGL::SyncViewport(OpenGLState& current_state) {
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void RasterizerOpenGL::SyncViewport(OpenGLState& current_state) {
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const auto& regs = system.GPU().Maxwell3D().regs;
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const auto& regs = system.GPU().Maxwell3D().regs;
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const bool geometry_shaders_enabled =
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const bool geometry_shaders_enabled =
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@ -146,6 +146,8 @@ private:
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const Tegra::Texture::FullTextureInfo& texture,
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const Tegra::Texture::FullTextureInfo& texture,
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const GLShader::SamplerEntry& entry);
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const GLShader::SamplerEntry& entry);
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void SetupComputeImages(const Shader& shader);
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/// Syncs the viewport and depth range to match the guest state
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/// Syncs the viewport and depth range to match the guest state
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void SyncViewport(OpenGLState& current_state);
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void SyncViewport(OpenGLState& current_state);
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@ -303,6 +303,10 @@ public:
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return is_bindless;
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return is_bindless;
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}
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}
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std::pair<u32, u32> GetBindlessCBuf() const {
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return {static_cast<u32>(offset >> 32), static_cast<u32>(offset)};
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}
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bool operator<(const Image& rhs) const {
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bool operator<(const Image& rhs) const {
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return std::tie(offset, index, type, is_bindless) <
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return std::tie(offset, index, type, is_bindless) <
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std::tie(rhs.offset, rhs.index, rhs.type, rhs.is_bindless);
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std::tie(rhs.offset, rhs.index, rhs.type, rhs.is_bindless);
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