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Assert Control Flow Instructions using Control Codes
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@ -1232,6 +1232,7 @@ union Instruction {
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BitField<60, 1, u64> is_b_gpr;
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BitField<59, 1, u64> is_c_gpr;
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BitField<20, 24, s64> smem_imm;
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BitField<0, 5, ControlCode> flow_control_code;
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Attribute attribute;
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Sampler sampler;
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@ -1658,4 +1659,4 @@ private:
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}
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};
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} // namespace Tegra::Shader
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} // namespace Tegra::Shader
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@ -3375,6 +3375,12 @@ private:
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EmitFragmentOutputsWrite();
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}
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const Tegra::Shader::ControlCode cc = instr.flow_control_code;
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if (cc != Tegra::Shader::ControlCode::T) {
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LOG_CRITICAL(HW_GPU, "EXIT Control Code used: {}", static_cast<u32>(cc));
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UNREACHABLE();
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}
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switch (instr.flow.cond) {
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case Tegra::Shader::FlowCondition::Always:
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shader.AddLine("return true;");
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@ -3404,6 +3410,11 @@ private:
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// Enclose "discard" in a conditional, so that GLSL compilation does not complain
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// about unexecuted instructions that may follow this.
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const Tegra::Shader::ControlCode cc = instr.flow_control_code;
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if (cc != Tegra::Shader::ControlCode::T) {
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LOG_CRITICAL(HW_GPU, "KIL Control Code used: {}", static_cast<u32>(cc));
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UNREACHABLE();
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}
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shader.AddLine("if (true) {");
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++shader.scope;
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shader.AddLine("discard;");
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@ -3461,6 +3472,11 @@ private:
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case OpCode::Id::BRA: {
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ASSERT_MSG(instr.bra.constant_buffer == 0,
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"BRA with constant buffers are not implemented");
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const Tegra::Shader::ControlCode cc = instr.flow_control_code;
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if (cc != Tegra::Shader::ControlCode::T) {
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LOG_CRITICAL(HW_GPU, "BRA Control Code used: {}", static_cast<u32>(cc));
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UNREACHABLE();
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}
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const u32 target = offset + instr.bra.GetBranchTarget();
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shader.AddLine("{ jmp_to = " + std::to_string(target) + "u; break; }");
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break;
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@ -3501,13 +3517,21 @@ private:
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}
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case OpCode::Id::SYNC: {
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// The SYNC opcode jumps to the address previously set by the SSY opcode
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ASSERT(instr.flow.cond == Tegra::Shader::FlowCondition::Always);
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const Tegra::Shader::ControlCode cc = instr.flow_control_code;
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if (cc != Tegra::Shader::ControlCode::T) {
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LOG_CRITICAL(HW_GPU, "SYNC Control Code used: {}", static_cast<u32>(cc));
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UNREACHABLE();
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}
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EmitPopFromFlowStack();
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break;
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}
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case OpCode::Id::BRK: {
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// The BRK opcode jumps to the address previously set by the PBK opcode
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ASSERT(instr.flow.cond == Tegra::Shader::FlowCondition::Always);
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const Tegra::Shader::ControlCode cc = instr.flow_control_code;
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if (cc != Tegra::Shader::ControlCode::T) {
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LOG_CRITICAL(HW_GPU, "BRK Control Code used: {}", static_cast<u32>(cc));
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UNREACHABLE();
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}
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EmitPopFromFlowStack();
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break;
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}
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