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Merge pull request #3578 from ReinUsesLisp/vmnmx
shader/video: Partially implement VMNMX
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commit
3d91dbb21d
@ -290,6 +290,23 @@ enum class VmadShr : u64 {
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Shr15 = 2,
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};
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enum class VmnmxType : u64 {
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Bits8,
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Bits16,
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Bits32,
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};
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enum class VmnmxOperation : u64 {
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Mrg_16H = 0,
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Mrg_16L = 1,
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Mrg_8B0 = 2,
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Mrg_8B2 = 3,
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Acc = 4,
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Min = 5,
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Max = 6,
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Nop = 7,
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};
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enum class XmadMode : u64 {
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None = 0,
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CLo = 1,
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@ -1650,6 +1667,42 @@ union Instruction {
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BitField<47, 1, u64> cc;
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} vmad;
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union {
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BitField<54, 1, u64> is_dest_signed;
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BitField<48, 1, u64> is_src_a_signed;
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BitField<49, 1, u64> is_src_b_signed;
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BitField<37, 2, u64> src_format_a;
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BitField<29, 2, u64> src_format_b;
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BitField<56, 1, u64> mx;
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BitField<55, 1, u64> sat;
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BitField<36, 2, u64> selector_a;
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BitField<28, 2, u64> selector_b;
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BitField<50, 1, u64> is_op_b_register;
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BitField<51, 3, VmnmxOperation> operation;
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VmnmxType SourceFormatA() const {
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switch (src_format_a) {
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case 0b11:
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return VmnmxType::Bits32;
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case 0b10:
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return VmnmxType::Bits16;
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default:
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return VmnmxType::Bits8;
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}
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}
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VmnmxType SourceFormatB() const {
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switch (src_format_b) {
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case 0b11:
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return VmnmxType::Bits32;
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case 0b10:
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return VmnmxType::Bits16;
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default:
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return VmnmxType::Bits8;
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}
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}
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} vmnmx;
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union {
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BitField<20, 16, u64> imm20_16;
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BitField<35, 1, u64> high_b_rr; // used on RR
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@ -1763,6 +1816,7 @@ public:
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MEMBAR,
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VMAD,
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VSETP,
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VMNMX,
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FFMA_IMM, // Fused Multiply and Add
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FFMA_CR,
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FFMA_RC,
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@ -2070,6 +2124,7 @@ private:
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INST("1110111110011---", Id::MEMBAR, Type::Trivial, "MEMBAR"),
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INST("01011111--------", Id::VMAD, Type::Video, "VMAD"),
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INST("0101000011110---", Id::VSETP, Type::Video, "VSETP"),
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INST("0011101---------", Id::VMNMX, Type::Video, "VMNMX"),
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INST("0011001-1-------", Id::FFMA_IMM, Type::Ffma, "FFMA_IMM"),
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INST("010010011-------", Id::FFMA_CR, Type::Ffma, "FFMA_CR"),
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INST("010100011-------", Id::FFMA_RC, Type::Ffma, "FFMA_RC"),
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@ -2170,7 +2225,7 @@ private:
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INST("0011011-11111---", Id::SHF_LEFT_IMM, Type::Shift, "SHF_LEFT_IMM"),
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INST("0100110011100---", Id::I2I_C, Type::Conversion, "I2I_C"),
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INST("0101110011100---", Id::I2I_R, Type::Conversion, "I2I_R"),
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INST("0011101-11100---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
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INST("0011100-11100---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
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INST("0100110010111---", Id::I2F_C, Type::Conversion, "I2F_C"),
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INST("0101110010111---", Id::I2F_R, Type::Conversion, "I2F_R"),
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INST("0011100-10111---", Id::I2F_IMM, Type::Conversion, "I2F_IMM"),
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@ -10,16 +10,24 @@
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namespace VideoCommon::Shader {
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using std::move;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Pred;
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using Tegra::Shader::VideoType;
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using Tegra::Shader::VmadShr;
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using Tegra::Shader::VmnmxOperation;
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using Tegra::Shader::VmnmxType;
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u32 ShaderIR::DecodeVideo(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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if (opcode->get().GetId() == OpCode::Id::VMNMX) {
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DecodeVMNMX(bb, instr);
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return pc;
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}
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const Node op_a =
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GetVideoOperand(GetRegister(instr.gpr8), instr.video.is_byte_chunk_a, instr.video.signed_a,
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instr.video.type_a, instr.video.byte_height_a);
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@ -109,4 +117,54 @@ Node ShaderIR::GetVideoOperand(Node op, bool is_chunk, bool is_signed,
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}
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}
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void ShaderIR::DecodeVMNMX(NodeBlock& bb, Tegra::Shader::Instruction instr) {
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UNIMPLEMENTED_IF(!instr.vmnmx.is_op_b_register);
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UNIMPLEMENTED_IF(instr.vmnmx.SourceFormatA() != VmnmxType::Bits32);
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UNIMPLEMENTED_IF(instr.vmnmx.SourceFormatB() != VmnmxType::Bits32);
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UNIMPLEMENTED_IF(instr.vmnmx.is_src_a_signed != instr.vmnmx.is_src_b_signed);
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UNIMPLEMENTED_IF(instr.vmnmx.sat);
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UNIMPLEMENTED_IF(instr.generates_cc);
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Node op_a = GetRegister(instr.gpr8);
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Node op_b = GetRegister(instr.gpr20);
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Node op_c = GetRegister(instr.gpr39);
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const bool is_oper1_signed = instr.vmnmx.is_src_a_signed; // Stubbed
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const bool is_oper2_signed = instr.vmnmx.is_dest_signed;
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const auto operation_a = instr.vmnmx.mx ? OperationCode::IMax : OperationCode::IMin;
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Node value = SignedOperation(operation_a, is_oper1_signed, move(op_a), move(op_b));
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switch (instr.vmnmx.operation) {
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case VmnmxOperation::Mrg_16H:
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value = BitfieldInsert(move(op_c), move(value), 16, 16);
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break;
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case VmnmxOperation::Mrg_16L:
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value = BitfieldInsert(move(op_c), move(value), 0, 16);
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break;
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case VmnmxOperation::Mrg_8B0:
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value = BitfieldInsert(move(op_c), move(value), 0, 8);
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break;
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case VmnmxOperation::Mrg_8B2:
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value = BitfieldInsert(move(op_c), move(value), 16, 8);
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break;
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case VmnmxOperation::Acc:
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value = Operation(OperationCode::IAdd, move(value), move(op_c));
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break;
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case VmnmxOperation::Min:
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value = SignedOperation(OperationCode::IMin, is_oper2_signed, move(value), move(op_c));
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break;
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case VmnmxOperation::Max:
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value = SignedOperation(OperationCode::IMax, is_oper2_signed, move(value), move(op_c));
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break;
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case VmnmxOperation::Nop:
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break;
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default:
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UNREACHABLE();
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break;
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}
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SetRegister(bb, instr.gpr0, move(value));
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}
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} // namespace VideoCommon::Shader
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@ -354,6 +354,9 @@ private:
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/// Marks the usage of a input or output attribute.
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void MarkAttributeUsage(Tegra::Shader::Attribute::Index index, u64 element);
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/// Decodes VMNMX instruction and inserts its code into the passed basic block.
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void DecodeVMNMX(NodeBlock& bb, Tegra::Shader::Instruction instr);
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void WriteTexInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
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const Node4& components);
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