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Merge pull request #392 from lioncash/sm
dyncom: Implement SMMLA/SMMUL/SMMLS
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commit
3e230d6c9e
@ -2358,13 +2358,41 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index)
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inst_base->load_r15 = 1;
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLALXY"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLALD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLAW"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlsld)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLSLD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMMLA"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smmls)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMMLS"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smmul)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMMUL"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst));
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smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->m = BIT(inst, 5);
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inst_cream->Ra = BITS(inst, 12, 15);
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inst_cream->Rm = BITS(inst, 8, 11);
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inst_cream->Rn = BITS(inst, 0, 3);
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inst_cream->Rd = BITS(inst, 16, 19);
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inst_cream->op1 = BITS(inst, 20, 22);
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inst_cream->op2 = BITS(inst, 5, 7);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smmls)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(smmla)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smmul)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(smmla)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smul)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smul_inst));
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@ -5494,9 +5522,42 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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SMLALD_INST:
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SMLAW_INST:
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SMLSLD_INST:
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SMMLA_INST:
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SMMLS_INST:
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SMMUL_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
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const u32 rm_val = RM;
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const u32 rn_val = RN;
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const bool do_round = (inst_cream->m == 1);
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// Assume SMMUL by default.
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s64 result = (s64)(s32)rn_val * (s64)(s32)rm_val;
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if (inst_cream->Ra != 15) {
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const u32 ra_val = cpu->Reg[inst_cream->Ra];
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// SMMLA, otherwise SMMLS
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if (BIT(inst_cream->op2, 1) == 0)
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result += ((s64)ra_val << 32);
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else
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result = ((s64)ra_val << 32) - result;
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}
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if (do_round)
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result += 0x80000000;
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RD = ((result >> 32) & 0xFFFFFFFF);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(smlad_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SMUL_INST:
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{
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