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https://github.com/yuzu-emu/yuzu.git
synced 2024-08-22 10:13:23 +02:00
Implement SetLcdForceBlack, move register enum to hw.h
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parent
8e4e28aacb
commit
47010fea31
@ -7,7 +7,9 @@
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#include "core/mem_map.h"
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#include "core/hle/kernel/event.h"
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#include "core/hle/kernel/shared_memory.h"
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#include "core/hle/result.h"
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#include "gsp_gpu.h"
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#include "core/hw/hw.h"
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#include "core/hw/gpu.h"
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#include "video_core/gpu_debugger.h"
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@ -85,7 +87,7 @@ static void WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* data) {
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return;
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while (size_in_bytes > 0) {
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GPU::Write<u32>(base_address + 0x1EB00000, *data);
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HW::Write<u32>(base_address + 0x1EB00000, *data);
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size_in_bytes -= 4;
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++data;
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@ -131,12 +133,12 @@ static void WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, const u32*
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const u32 reg_address = base_address + 0x1EB00000;
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u32 reg_value;
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GPU::Read<u32>(reg_value, reg_address);
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HW::Read<u32>(reg_value, reg_address);
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// Update the current value of the register only for set mask bits
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reg_value = (reg_value & ~*masks) | (*data | *masks);
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GPU::Write<u32>(reg_address, reg_value);
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HW::Write<u32>(reg_address, reg_value);
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size_in_bytes -= 4;
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++data;
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@ -188,7 +190,7 @@ static void ReadHWRegs(Service::Interface* self) {
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u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
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while (size > 0) {
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GPU::Read<u32>(*dst, reg_addr + 0x1EB00000);
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HW::Read<u32>(*dst, reg_addr + 0x1EB00000);
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size -= 4;
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++dst;
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@ -427,6 +429,38 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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}
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}
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/**
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* GSP_GPU::SetLcdForceBlack service function
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*
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* Enable or disable REG_LCDCOLORFILL with the color black.
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*
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* Inputs:
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* 1: Black color fill flag (0 = don't fill, !0 = fill)
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* Outputs:
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* 1: Result code
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*/
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void SetLcdForceBlack(Service::Interface* self) {
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// TODO: currently has no effect, as LCD reg writes have nowhere to go.
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u32* cmd_buff = Kernel::GetCommandBuffer();
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bool enable_black = cmd_buff[1] != 0;
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u32 data = 0;
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if (enable_black) {
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// Sets bit 24 to 1, enabling the fill
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// Since data is already 0x00000000, there is no need to explicitly set
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// bits 0-23 to zero (black), or bit 24 to 0 (fill disabled).
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data |= (1 << 24);
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}
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u32 data_main = data;
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u32 data_sub = data;
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WriteHWRegs(0x202204, 4, &data_main); // Main LCD
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WriteHWRegs(0x202A04, 4, &data_sub); // Sub LCD
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cmd_buff[1] = RESULT_SUCCESS.raw;
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}
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/// This triggers handling of the GX command written to the command buffer in shared memory.
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static void TriggerCmdReqQueue(Service::Interface* self) {
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// Iterate through each thread's command queue...
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@ -460,7 +494,7 @@ const Interface::FunctionInfo FunctionTable[] = {
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{0x00080082, FlushDataCache, "FlushDataCache"},
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{0x00090082, nullptr, "InvalidateDataCache"},
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{0x000A0044, nullptr, "RegisterInterruptEvents"},
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{0x000B0040, nullptr, "SetLcdForceBlack"},
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{0x000B0040, SetLcdForceBlack, "SetLcdForceBlack"},
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{0x000C0000, TriggerCmdReqQueue, "TriggerCmdReqQueue"},
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{0x000D0140, nullptr, "SetDisplayTransfer"},
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{0x000E0180, nullptr, "SetTextureCopy"},
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@ -15,12 +15,13 @@
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#include "core/hle/service/gsp_gpu.h"
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#include "core/hle/service/dsp_dsp.h"
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#include "core/hw/hw.h"
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#include "core/hw/gpu.h"
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#include "video_core/command_processor.h"
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#include "video_core/utils.h"
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#include "video_core/video_core.h"
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#include <video_core/color.h>
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#include "video_core/color.h"
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namespace GPU {
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@ -40,7 +41,7 @@ static bool last_skip_frame = false;
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template <typename T>
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inline void Read(T &var, const u32 raw_addr) {
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u32 addr = raw_addr - 0x1EF00000;
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u32 addr = raw_addr - HW::VADDR_GPU;
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u32 index = addr / 4;
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// Reads other than u32 are untested, so I'd rather have them abort than silently fail
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@ -54,7 +55,7 @@ inline void Read(T &var, const u32 raw_addr) {
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template <typename T>
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inline void Write(u32 addr, const T data) {
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addr -= 0x1EF00000;
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addr -= HW::VADDR_GPU;
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u32 index = addr / 4;
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// Writes other than u32 are untested, so I'd rather have them abort than silently fail
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@ -313,8 +314,6 @@ void Init() {
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framebuffer_top.address_right2 = 0x182B9800;
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framebuffer_sub.address_left1 = 0x1848F000;
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framebuffer_sub.address_left2 = 0x184C7800;
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//framebuffer_sub.address_right1 = unknown;
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//framebuffer_sub.address_right2 = unknown;
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framebuffer_top.width = 240;
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framebuffer_top.height = 400;
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@ -9,32 +9,6 @@
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namespace HW {
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enum {
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VADDR_HASH = 0x1EC01000,
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VADDR_CSND = 0x1EC03000,
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VADDR_DSP = 0x1EC40000,
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VADDR_PDN = 0x1EC41000,
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VADDR_CODEC = 0x1EC41000,
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VADDR_SPI = 0x1EC42000,
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VADDR_SPI_2 = 0x1EC43000, // Only used under TWL_FIRM?
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VADDR_I2C = 0x1EC44000,
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VADDR_CODEC_2 = 0x1EC45000,
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VADDR_HID = 0x1EC46000,
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VADDR_PAD = 0x1EC46000,
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VADDR_PTM = 0x1EC46000,
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VADDR_GPIO = 0x1EC47000,
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VADDR_I2C_2 = 0x1EC48000,
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VADDR_SPI_3 = 0x1EC60000,
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VADDR_I2C_3 = 0x1EC61000,
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VADDR_MIC = 0x1EC62000,
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VADDR_PXI = 0x1EC63000, // 0xFFFD2000
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//VADDR_NTRCARD
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VADDR_CDMA = 0xFFFDA000, // CoreLink DMA-330? Info
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VADDR_DSP_2 = 0x1ED03000,
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VADDR_HASH_2 = 0x1EE01000,
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VADDR_GPU = 0x1EF00000,
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};
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template <typename T>
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inline void Read(T &var, const u32 addr) {
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switch (addr & 0xFFFFF000) {
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@ -8,6 +8,32 @@
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namespace HW {
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enum {
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VADDR_IO = 0x1EC00000,
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VADDR_HASH = 0x1EC01000,
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VADDR_CSND = 0x1EC03000,
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VADDR_DSP = 0x1EC40000,
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VADDR_PDN = 0x1EC41000,
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VADDR_CODEC = 0x1EC41000,
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VADDR_SPI = 0x1EC42000,
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VADDR_SPI_2 = 0x1EC43000, // Only used under TWL_FIRM?
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VADDR_I2C = 0x1EC44000,
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VADDR_CODEC_2 = 0x1EC45000,
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VADDR_HID = 0x1EC46000,
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VADDR_GPIO = 0x1EC47000,
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VADDR_I2C_2 = 0x1EC48000,
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VADDR_SPI_3 = 0x1EC60000,
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VADDR_I2C_3 = 0x1EC61000,
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VADDR_MIC = 0x1EC62000,
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VADDR_PXI = 0x1EC63000, // 0xFFFD2000
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//VADDR_NTRCARD
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VADDR_CDMA = 0xFFFDA000, // CoreLink DMA-330? Info
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VADDR_LCD = 0x1ED02000,
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VADDR_DSP_2 = 0x1ED03000,
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VADDR_HASH_2 = 0x1EE01000,
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VADDR_GPU = 0x1EF00000,
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};
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template <typename T>
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void Read(T &var, const u32 addr);
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