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Merge pull request #1517 from bunnei/dma
GPU/DMA: Flush the source region and invalidate the destination region when doing a DMA transfer.
This commit is contained in:
commit
4849569565
@ -47,9 +47,12 @@ void Fermi2D::HandleSurfaceCopy() {
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u32 dst_bytes_per_pixel = RenderTargetBytesPerPixel(regs.dst.format);
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if (!rasterizer.AccelerateSurfaceCopy(regs.src, regs.dst)) {
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// TODO(bunnei): The below implementation currently will not get hit, as
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// AccelerateSurfaceCopy tries to always copy and will always return success. This should be
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// changed once we properly support flushing.
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rasterizer.FlushRegion(source_cpu, src_bytes_per_pixel * regs.src.width * regs.src.height);
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// We have to invalidate the destination region to evict any outdated surfaces from the
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// cache. We do this before actually writing the new data because the destination address
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// might contain a dirty surface that will have to be written back to memory.
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rasterizer.InvalidateRegion(dest_cpu,
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dst_bytes_per_pixel * regs.dst.width * regs.dst.height);
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if (regs.src.linear == regs.dst.linear) {
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// If the input layout and the output layout are the same, just perform a raw copy.
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@ -5,10 +5,14 @@
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#include "common/logging/log.h"
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#include "core/memory.h"
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#include "video_core/engines/kepler_memory.h"
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#include "video_core/rasterizer_interface.h"
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namespace Tegra::Engines {
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KeplerMemory::KeplerMemory(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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KeplerMemory::KeplerMemory(VideoCore::RasterizerInterface& rasterizer,
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MemoryManager& memory_manager)
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: memory_manager(memory_manager), rasterizer{rasterizer} {}
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KeplerMemory::~KeplerMemory() = default;
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void KeplerMemory::WriteReg(u32 method, u32 value) {
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@ -37,6 +41,11 @@ void KeplerMemory::ProcessData(u32 data) {
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VAddr dest_address =
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*memory_manager.GpuToCpuAddress(address + state.write_offset * sizeof(u32));
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// We have to invalidate the destination region to evict any outdated surfaces from the cache.
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// We do this before actually writing the new data because the destination address might contain
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// a dirty surface that will have to be written back to memory.
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rasterizer.InvalidateRegion(dest_address, sizeof(u32));
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Memory::Write32(dest_address, data);
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state.write_offset++;
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@ -11,6 +11,10 @@
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#include "common/common_types.h"
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#include "video_core/memory_manager.h"
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namespace VideoCore {
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class RasterizerInterface;
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}
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namespace Tegra::Engines {
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#define KEPLERMEMORY_REG_INDEX(field_name) \
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@ -18,7 +22,7 @@ namespace Tegra::Engines {
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class KeplerMemory final {
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public:
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KeplerMemory(MemoryManager& memory_manager);
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KeplerMemory(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager);
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~KeplerMemory();
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/// Write the value to the register identified by method.
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@ -72,6 +76,7 @@ public:
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private:
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MemoryManager& memory_manager;
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VideoCore::RasterizerInterface& rasterizer;
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void ProcessData(u32 data);
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};
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@ -4,12 +4,14 @@
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#include "core/memory.h"
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra {
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namespace Engines {
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MaxwellDMA::MaxwellDMA(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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MaxwellDMA::MaxwellDMA(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager)
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: memory_manager(memory_manager), rasterizer{rasterizer} {}
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void MaxwellDMA::WriteReg(u32 method, u32 value) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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@ -44,38 +46,79 @@ void MaxwellDMA::HandleCopy() {
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ASSERT(regs.exec.query_mode == Regs::QueryMode::None);
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ASSERT(regs.exec.query_intr == Regs::QueryIntr::None);
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ASSERT(regs.exec.copy_mode == Regs::CopyMode::Unk2);
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ASSERT(regs.src_params.pos_x == 0);
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ASSERT(regs.src_params.pos_y == 0);
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ASSERT(regs.dst_params.pos_x == 0);
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ASSERT(regs.dst_params.pos_y == 0);
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if (regs.exec.is_dst_linear == regs.exec.is_src_linear) {
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std::size_t copy_size = regs.x_count;
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if (!regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
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// If both the source and the destination are in block layout, assert.
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UNREACHABLE_MSG("Tiled->Tiled DMA transfers are not yet implemented");
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return;
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}
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if (regs.exec.is_dst_linear && regs.exec.is_src_linear) {
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// When the enable_2d bit is disabled, the copy is performed as if we were copying a 1D
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// buffer of length `x_count`, otherwise we copy a 2D buffer of size (x_count, y_count).
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if (regs.exec.enable_2d) {
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copy_size = copy_size * regs.y_count;
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// buffer of length `x_count`, otherwise we copy a 2D image of dimensions (x_count,
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// y_count).
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if (!regs.exec.enable_2d) {
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Memory::CopyBlock(dest_cpu, source_cpu, regs.x_count);
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return;
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}
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Memory::CopyBlock(dest_cpu, source_cpu, copy_size);
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// If both the source and the destination are in linear layout, perform a line-by-line
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// copy. We're going to take a subrect of size (x_count, y_count) from the source
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// rectangle. There is no need to manually flush/invalidate the regions because
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// CopyBlock does that for us.
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for (u32 line = 0; line < regs.y_count; ++line) {
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const VAddr source_line = source_cpu + line * regs.src_pitch;
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const VAddr dest_line = dest_cpu + line * regs.dst_pitch;
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Memory::CopyBlock(dest_line, source_line, regs.x_count);
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}
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return;
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}
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ASSERT(regs.exec.enable_2d == 1);
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std::size_t copy_size = regs.x_count * regs.y_count;
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const auto FlushAndInvalidate = [&](u32 src_size, u32 dst_size) {
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// TODO(Subv): For now, manually flush the regions until we implement GPU-accelerated
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// copying.
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rasterizer.FlushRegion(source_cpu, src_size);
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// We have to invalidate the destination region to evict any outdated surfaces from the
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// cache. We do this before actually writing the new data because the destination address
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// might contain a dirty surface that will have to be written back to memory.
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rasterizer.InvalidateRegion(dest_cpu, dst_size);
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};
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u8* src_buffer = Memory::GetPointer(source_cpu);
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u8* dst_buffer = Memory::GetPointer(dest_cpu);
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if (regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
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ASSERT(regs.src_params.size_z == 1);
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// If the input is tiled and the output is linear, deswizzle the input and copy it over.
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Texture::CopySwizzledData(regs.src_params.size_x, regs.src_params.size_y,
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regs.src_params.size_z, 1, 1, src_buffer, dst_buffer, true,
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regs.src_params.BlockHeight(), regs.src_params.BlockDepth());
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u32 src_bytes_per_pixel = regs.src_pitch / regs.src_params.size_x;
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FlushAndInvalidate(regs.src_pitch * regs.src_params.size_y,
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copy_size * src_bytes_per_pixel);
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Texture::UnswizzleSubrect(regs.x_count, regs.y_count, regs.dst_pitch,
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regs.src_params.size_x, src_bytes_per_pixel, source_cpu, dest_cpu,
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regs.src_params.BlockHeight(), regs.src_params.pos_x,
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regs.src_params.pos_y);
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} else {
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ASSERT(regs.dst_params.size_z == 1);
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ASSERT(regs.src_pitch == regs.x_count);
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u32 src_bpp = regs.src_pitch / regs.x_count;
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FlushAndInvalidate(regs.src_pitch * regs.y_count,
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regs.dst_params.size_x * regs.dst_params.size_y * src_bpp);
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// If the input is linear and the output is tiled, swizzle the input and copy it over.
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Texture::CopySwizzledData(regs.dst_params.size_x, regs.dst_params.size_y,
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regs.dst_params.size_z, 1, 1, dst_buffer, src_buffer, false,
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regs.dst_params.BlockHeight(), regs.dst_params.BlockDepth());
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Texture::SwizzleSubrect(regs.x_count, regs.y_count, regs.src_pitch, regs.dst_params.size_x,
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src_bpp, dest_cpu, source_cpu, regs.dst_params.BlockHeight());
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}
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}
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@ -12,11 +12,15 @@
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#include "video_core/gpu.h"
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#include "video_core/memory_manager.h"
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namespace VideoCore {
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class RasterizerInterface;
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}
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namespace Tegra::Engines {
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class MaxwellDMA final {
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public:
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explicit MaxwellDMA(MemoryManager& memory_manager);
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explicit MaxwellDMA(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager);
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~MaxwellDMA() = default;
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/// Write the value to the register identified by method.
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@ -133,6 +137,8 @@ public:
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MemoryManager& memory_manager;
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private:
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VideoCore::RasterizerInterface& rasterizer;
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/// Performs the copy from the source buffer to the destination buffer as configured in the
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/// registers.
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void HandleCopy();
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@ -27,8 +27,8 @@ GPU::GPU(VideoCore::RasterizerInterface& rasterizer) {
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maxwell_3d = std::make_unique<Engines::Maxwell3D>(rasterizer, *memory_manager);
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fermi_2d = std::make_unique<Engines::Fermi2D>(rasterizer, *memory_manager);
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maxwell_compute = std::make_unique<Engines::MaxwellCompute>();
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maxwell_dma = std::make_unique<Engines::MaxwellDMA>(*memory_manager);
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kepler_memory = std::make_unique<Engines::KeplerMemory>(*memory_manager);
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maxwell_dma = std::make_unique<Engines::MaxwellDMA>(rasterizer, *memory_manager);
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kepler_memory = std::make_unique<Engines::KeplerMemory>(rasterizer, *memory_manager);
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}
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GPU::~GPU() = default;
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@ -659,6 +659,12 @@ void RasterizerOpenGL::FlushAndInvalidateRegion(VAddr addr, u64 size) {
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bool RasterizerOpenGL::AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Regs::Surface& src,
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const Tegra::Engines::Fermi2D::Regs::Surface& dst) {
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MICROPROFILE_SCOPE(OpenGL_Blits);
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if (Settings::values.use_accurate_gpu_emulation) {
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// Skip the accelerated copy and perform a slow but more accurate copy
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return false;
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}
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res_cache.FermiCopySurface(src, dst);
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return true;
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}
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@ -237,6 +237,46 @@ std::vector<u8> UnswizzleTexture(VAddr address, u32 tile_size, u32 bytes_per_pix
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return unswizzled_data;
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}
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void SwizzleSubrect(u32 subrect_width, u32 subrect_height, u32 source_pitch, u32 swizzled_width,
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u32 bytes_per_pixel, VAddr swizzled_data, VAddr unswizzled_data,
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u32 block_height) {
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const u32 image_width_in_gobs{(swizzled_width * bytes_per_pixel + 63) / 64};
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for (u32 line = 0; line < subrect_height; ++line) {
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const u32 gob_address_y =
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(line / (8 * block_height)) * 512 * block_height * image_width_in_gobs +
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(line % (8 * block_height) / 8) * 512;
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const auto& table = legacy_swizzle_table[line % 8];
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for (u32 x = 0; x < subrect_width; ++x) {
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const u32 gob_address = gob_address_y + (x * bytes_per_pixel / 64) * 512 * block_height;
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const u32 swizzled_offset = gob_address + table[(x * bytes_per_pixel) % 64];
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const VAddr source_line = unswizzled_data + line * source_pitch + x * bytes_per_pixel;
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const VAddr dest_addr = swizzled_data + swizzled_offset;
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Memory::CopyBlock(dest_addr, source_line, bytes_per_pixel);
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}
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}
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}
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void UnswizzleSubrect(u32 subrect_width, u32 subrect_height, u32 dest_pitch, u32 swizzled_width,
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u32 bytes_per_pixel, VAddr swizzled_data, VAddr unswizzled_data,
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u32 block_height, u32 offset_x, u32 offset_y) {
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for (u32 line = 0; line < subrect_height; ++line) {
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const u32 y2 = line + offset_y;
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const u32 gob_address_y =
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(y2 / (8 * block_height)) * 512 * block_height + (y2 % (8 * block_height) / 8) * 512;
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const auto& table = legacy_swizzle_table[y2 % 8];
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for (u32 x = 0; x < subrect_width; ++x) {
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const u32 x2 = (x + offset_x) * bytes_per_pixel;
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const u32 gob_address = gob_address_y + (x2 / 64) * 512 * block_height;
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const u32 swizzled_offset = gob_address + table[x2 % 64];
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const VAddr dest_line = unswizzled_data + line * dest_pitch + x * bytes_per_pixel;
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const VAddr source_addr = swizzled_data + swizzled_offset;
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Memory::CopyBlock(dest_line, source_addr, bytes_per_pixel);
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}
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}
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}
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std::vector<u8> DecodeTexture(const std::vector<u8>& texture_data, TextureFormat format, u32 width,
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u32 height) {
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std::vector<u8> rgba_data;
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@ -35,4 +35,13 @@ std::vector<u8> DecodeTexture(const std::vector<u8>& texture_data, TextureFormat
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std::size_t CalculateSize(bool tiled, u32 bytes_per_pixel, u32 width, u32 height, u32 depth,
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u32 block_height, u32 block_depth);
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/// Copies an untiled subrectangle into a tiled surface.
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void SwizzleSubrect(u32 subrect_width, u32 subrect_height, u32 source_pitch, u32 swizzled_width,
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u32 bytes_per_pixel, VAddr swizzled_data, VAddr unswizzled_data,
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u32 block_height);
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/// Copies a tiled subrectangle into a linear surface.
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void UnswizzleSubrect(u32 subrect_width, u32 subrect_height, u32 dest_pitch, u32 swizzled_width,
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u32 bytes_per_pixel, VAddr swizzled_data, VAddr unswizzled_data,
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u32 block_height, u32 offset_x, u32 offset_y);
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} // namespace Tegra::Texture
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