mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-08-21 00:33:21 +02:00
shader_recompiler, video_core: Resolve clang errors
Silences the following warnings-turned-errors: -Wsign-conversion -Wunused-private-field -Wbraced-scalar-init -Wunused-variable And some other errors
This commit is contained in:
parent
4e4b8775b5
commit
49946cf780
@ -59,7 +59,7 @@ public:
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}
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std::string code;
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RegAlloc reg_alloc{*this};
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RegAlloc reg_alloc{};
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const Info& info;
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const Profile& profile;
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const RuntimeInfo& runtime_info;
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@ -86,7 +86,7 @@ struct ScalarF64 : Value {};
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class RegAlloc {
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public:
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RegAlloc(EmitContext& ctx_) : ctx{ctx_} {}
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RegAlloc() = default;
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Register Define(IR::Inst& inst);
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@ -142,7 +142,6 @@ private:
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void Free(Id id);
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EmitContext& ctx;
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size_t num_used_registers{};
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size_t num_used_long_registers{};
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std::bitset<NUM_REGS> register_use{};
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@ -22,7 +22,7 @@ void Compare(EmitContext& ctx, IR::Inst& inst, std::string_view lhs, std::string
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}
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bool IsPrecise(const IR::Inst& inst) {
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return {inst.Flags<IR::FpControl>().no_contraction};
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return inst.Flags<IR::FpControl>().no_contraction;
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}
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} // Anonymous namespace
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@ -109,7 +109,7 @@ private:
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return;
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}
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if (offset.IsImmediate()) {
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Add(spv::ImageOperandsMask::ConstOffset, ctx.SConst(offset.U32()));
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Add(spv::ImageOperandsMask::ConstOffset, ctx.SConst(static_cast<s32>(offset.U32())));
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return;
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}
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IR::Inst* const inst{offset.InstRecursive()};
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@ -117,16 +117,21 @@ private:
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switch (inst->GetOpcode()) {
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case IR::Opcode::CompositeConstructU32x2:
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Add(spv::ImageOperandsMask::ConstOffset,
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ctx.SConst(inst->Arg(0).U32(), inst->Arg(1).U32()));
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ctx.SConst(static_cast<s32>(inst->Arg(0).U32()),
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static_cast<s32>(inst->Arg(1).U32())));
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return;
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case IR::Opcode::CompositeConstructU32x3:
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Add(spv::ImageOperandsMask::ConstOffset,
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ctx.SConst(inst->Arg(0).U32(), inst->Arg(1).U32(), inst->Arg(2).U32()));
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ctx.SConst(static_cast<s32>(inst->Arg(0).U32()),
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static_cast<s32>(inst->Arg(1).U32()),
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static_cast<s32>(inst->Arg(2).U32())));
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return;
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case IR::Opcode::CompositeConstructU32x4:
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Add(spv::ImageOperandsMask::ConstOffset,
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ctx.SConst(inst->Arg(0).U32(), inst->Arg(1).U32(), inst->Arg(2).U32(),
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inst->Arg(3).U32()));
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ctx.SConst(static_cast<s32>(inst->Arg(0).U32()),
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static_cast<s32>(inst->Arg(1).U32()),
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static_cast<s32>(inst->Arg(2).U32()),
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static_cast<s32>(inst->Arg(3).U32())));
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return;
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default:
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break;
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@ -67,7 +67,8 @@ constexpr OpcodeMeta META_TABLE[]{
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};
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constexpr size_t CalculateNumArgsOf(Opcode op) {
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const auto& arg_types{META_TABLE[static_cast<size_t>(op)].arg_types};
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return std::distance(arg_types.begin(), std::ranges::find(arg_types, Type::Void));
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return static_cast<size_t>(
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std::distance(arg_types.begin(), std::ranges::find(arg_types, Type::Void)));
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}
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constexpr u8 NUM_ARGS[]{
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@ -161,7 +161,6 @@ private:
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Environment& env;
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ObjectPool<Block>& block_pool;
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boost::container::small_vector<Function, 1> functions;
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FunctionId current_function_id{0};
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Location program_start;
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bool exits_to_dispatcher{};
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Block* dispatch_block{};
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@ -313,9 +313,7 @@ bool NeedsLift(Node goto_stmt, Node label_stmt) noexcept {
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class GotoPass {
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public:
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explicit GotoPass(Flow::CFG& cfg, ObjectPool<IR::Inst>& inst_pool_,
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ObjectPool<IR::Block>& block_pool_, ObjectPool<Statement>& stmt_pool)
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: inst_pool{inst_pool_}, block_pool{block_pool_}, pool{stmt_pool} {
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explicit GotoPass(Flow::CFG& cfg, ObjectPool<Statement>& stmt_pool) : pool{stmt_pool} {
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std::vector gotos{BuildTree(cfg)};
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for (const Node& goto_stmt : gotos | std::views::reverse) {
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RemoveGoto(goto_stmt);
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@ -616,8 +614,6 @@ private:
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return parent_tree.insert(std::next(loop), *new_goto);
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}
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ObjectPool<IR::Inst>& inst_pool;
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ObjectPool<IR::Block>& block_pool;
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ObjectPool<Statement>& pool;
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Statement root_stmt{FunctionTag{}};
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};
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@ -864,7 +860,6 @@ private:
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ObjectPool<IR::Block>& block_pool;
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Environment& env;
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IR::AbstractSyntaxList& syntax_list;
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u32 loop_id{};
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// TODO: C++20 Remove this when all compilers support constexpr std::vector
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#if __cpp_lib_constexpr_vector >= 201907
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@ -878,7 +873,7 @@ private:
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IR::AbstractSyntaxList BuildASL(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Block>& block_pool,
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Environment& env, Flow::CFG& cfg) {
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ObjectPool<Statement> stmt_pool{64};
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GotoPass goto_pass{cfg, inst_pool, block_pool, stmt_pool};
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GotoPass goto_pass{cfg, stmt_pool};
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Statement& root{goto_pass.RootStatement()};
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IR::AbstractSyntaxList syntax_list;
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TranslatePass{inst_pool, block_pool, stmt_pool, env, root, syntax_list};
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@ -59,14 +59,14 @@ IR::U32U64 ApplyIntegerAtomOp(IR::IREmitter& ir, const IR::U32U64& offset, const
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IR::Value ApplyFpAtomOp(IR::IREmitter& ir, const IR::U64& offset, const IR::Value& op_b, AtomOp op,
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AtomSize size) {
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static constexpr IR::FpControl f16_control{
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.no_contraction{false},
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.rounding{IR::FpRounding::RN},
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.fmz_mode{IR::FmzMode::DontCare},
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.no_contraction = false,
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.rounding = IR::FpRounding::RN,
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.fmz_mode = IR::FmzMode::DontCare,
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};
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static constexpr IR::FpControl f32_control{
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.no_contraction{false},
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.rounding{IR::FpRounding::RN},
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.fmz_mode{IR::FmzMode::FTZ},
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.no_contraction = false,
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.rounding = IR::FpRounding::RN,
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.fmz_mode = IR::FmzMode::FTZ,
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};
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switch (op) {
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case AtomOp::ADD:
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@ -104,7 +104,9 @@ void I2F(TranslatorVisitor& v, u64 insn, IR::U32U64 src) {
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.rounding = CastFpRounding(i2f.fp_rounding),
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.fmz_mode = IR::FmzMode::DontCare,
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};
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auto value{v.ir.ConvertIToF(dst_bitsize, conversion_src_bitsize, is_signed, src, fp_control)};
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auto value{v.ir.ConvertIToF(static_cast<size_t>(dst_bitsize),
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static_cast<size_t>(conversion_src_bitsize), is_signed, src,
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fp_control)};
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if (i2f.neg != 0) {
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if (i2f.abs != 0 || !is_signed) {
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// We know the value is positive
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@ -80,10 +80,10 @@ void TranslatorVisitor::ALD(u64 insn) {
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for (u32 element = 0; element < num_elements; ++element) {
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if (ald.patch != 0) {
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const IR::Patch patch{offset / 4 + element};
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F(ald.dest_reg + element, ir.GetPatch(patch));
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F(ald.dest_reg + static_cast<int>(element), ir.GetPatch(patch));
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} else {
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const IR::Attribute attr{offset / 4 + element};
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F(ald.dest_reg + element, ir.GetAttribute(attr, vertex));
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F(ald.dest_reg + static_cast<int>(element), ir.GetAttribute(attr, vertex));
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}
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}
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return;
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@ -92,7 +92,7 @@ void TranslatorVisitor::ALD(u64 insn) {
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throw NotImplementedException("Indirect patch read");
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}
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HandleIndexed(*this, ald.index_reg, num_elements, [&](u32 element, IR::U32 final_offset) {
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F(ald.dest_reg + element, ir.GetAttributeIndexed(final_offset, vertex));
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F(ald.dest_reg + static_cast<int>(element), ir.GetAttributeIndexed(final_offset, vertex));
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});
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}
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@ -121,10 +121,10 @@ void TranslatorVisitor::AST(u64 insn) {
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for (u32 element = 0; element < num_elements; ++element) {
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if (ast.patch != 0) {
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const IR::Patch patch{offset / 4 + element};
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ir.SetPatch(patch, F(ast.src_reg + element));
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ir.SetPatch(patch, F(ast.src_reg + static_cast<int>(element)));
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} else {
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const IR::Attribute attr{offset / 4 + element};
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ir.SetAttribute(attr, F(ast.src_reg + element), vertex);
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ir.SetAttribute(attr, F(ast.src_reg + static_cast<int>(element)), vertex);
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}
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}
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return;
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@ -133,7 +133,7 @@ void TranslatorVisitor::AST(u64 insn) {
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throw NotImplementedException("Indexed tessellation patch store");
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}
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HandleIndexed(*this, ast.index_reg, num_elements, [&](u32 element, IR::U32 final_offset) {
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ir.SetAttributeIndexed(final_offset, F(ast.src_reg + element), vertex);
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ir.SetAttributeIndexed(final_offset, F(ast.src_reg + static_cast<int>(element)), vertex);
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});
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}
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@ -69,9 +69,6 @@ TextureType GetType(Type type) {
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}
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IR::Value MakeCoords(TranslatorVisitor& v, IR::Reg reg, Type type) {
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const auto array{[&](int index) {
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return v.ir.BitFieldExtract(v.X(reg + index), v.ir.Imm32(0), v.ir.Imm32(16));
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}};
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switch (type) {
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case Type::_1D:
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case Type::BUFFER_1D:
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@ -160,10 +160,10 @@ unsigned SwizzleMask(u64 swizzle) {
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IR::Value MakeColor(IR::IREmitter& ir, IR::Reg reg, int num_regs) {
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std::array<IR::U32, 4> colors;
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for (int i = 0; i < num_regs; ++i) {
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colors[i] = ir.GetReg(reg + i);
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colors[static_cast<size_t>(i)] = ir.GetReg(reg + i);
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}
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for (int i = num_regs; i < 4; ++i) {
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colors[i] = ir.Imm32(0);
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colors[static_cast<size_t>(i)] = ir.Imm32(0);
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}
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return ir.CompositeConstruct(colors[0], colors[1], colors[2], colors[3]);
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}
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@ -211,12 +211,12 @@ void TranslatorVisitor::SULD(u64 insn) {
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if (is_typed) {
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const int num_regs{SizeInRegs(suld.size)};
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for (int i = 0; i < num_regs; ++i) {
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X(dest_reg + i, IR::U32{ir.CompositeExtract(result, i)});
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X(dest_reg + i, IR::U32{ir.CompositeExtract(result, static_cast<size_t>(i))});
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}
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} else {
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const unsigned mask{SwizzleMask(suld.swizzle)};
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const int bits{std::popcount(mask)};
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if (!IR::IsAligned(dest_reg, bits == 3 ? 4 : bits)) {
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if (!IR::IsAligned(dest_reg, bits == 3 ? 4 : static_cast<size_t>(bits))) {
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throw NotImplementedException("Unaligned destination register");
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}
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for (unsigned component = 0; component < 4; ++component) {
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@ -314,8 +314,8 @@ std::optional<StorageBufferAddr> Track(const IR::Value& value, const Bias* bias)
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return std::nullopt;
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}
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const StorageBufferAddr storage_buffer{
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.index{index.U32()},
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.offset{offset.U32()},
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.index = index.U32(),
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.offset = offset.U32(),
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};
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if (!Common::IsAligned(storage_buffer.offset, 16)) {
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// The SSBO pointer has to be aligned
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@ -484,7 +484,7 @@ void GlobalMemoryToStorageBufferPass(IR::Program& program) {
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.cbuf_index = storage_buffer.index,
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.cbuf_offset = storage_buffer.offset,
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.count = 1,
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.is_written{info.writes.contains(storage_buffer)},
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.is_written = info.writes.contains(storage_buffer),
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});
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}
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for (const StorageInst& storage_inst : info.to_replace) {
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@ -104,9 +104,7 @@ public:
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template <typename Spec>
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static auto MakeConfigureSpecFunc() {
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return [](GraphicsPipeline* pipeline, bool is_indexed) {
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pipeline->ConfigureImpl<Spec>(is_indexed);
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};
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return [](GraphicsPipeline* pl, bool is_indexed) { pl->ConfigureImpl<Spec>(is_indexed); };
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}
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private:
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