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https://github.com/yuzu-emu/yuzu.git
synced 2024-08-21 19:43:25 +02:00
Refactor access to state in shader-jit
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0d8bd3ba36
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4e01e9ffc5
@ -64,6 +64,7 @@ MICROPROFILE_DEFINE(GPU_Shader, "GPU", "Shader", MP_RGB(50, 50, 240));
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OutputVertex ShaderSetup::Run(UnitState<false>& state, const InputVertex& input, int num_attributes) {
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OutputVertex ShaderSetup::Run(UnitState<false>& state, const InputVertex& input, int num_attributes) {
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auto& config = g_state.regs.vs;
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auto& config = g_state.regs.vs;
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auto& setup = g_state.vs;
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MICROPROFILE_SCOPE(GPU_Shader);
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MICROPROFILE_SCOPE(GPU_Shader);
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@ -81,7 +82,7 @@ OutputVertex ShaderSetup::Run(UnitState<false>& state, const InputVertex& input,
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#ifdef ARCHITECTURE_x86_64
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#ifdef ARCHITECTURE_x86_64
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if (VideoCore::g_shader_jit_enabled)
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if (VideoCore::g_shader_jit_enabled)
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jit_shader->Run(&state.registers, g_state.regs.vs.main_offset);
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jit_shader->Run(setup, state, config.main_offset);
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else
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else
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RunInterpreter(state);
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RunInterpreter(state);
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#else
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#else
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@ -283,10 +283,10 @@ struct UnitState {
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static size_t InputOffset(const SourceRegister& reg) {
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static size_t InputOffset(const SourceRegister& reg) {
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switch (reg.GetRegisterType()) {
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switch (reg.GetRegisterType()) {
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case RegisterType::Input:
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case RegisterType::Input:
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return offsetof(UnitState::Registers, input) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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return offsetof(UnitState, registers.input) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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case RegisterType::Temporary:
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case RegisterType::Temporary:
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return offsetof(UnitState::Registers, temporary) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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return offsetof(UnitState, registers.temporary) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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default:
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default:
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UNREACHABLE();
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UNREACHABLE();
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@ -297,10 +297,10 @@ struct UnitState {
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static size_t OutputOffset(const DestRegister& reg) {
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static size_t OutputOffset(const DestRegister& reg) {
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switch (reg.GetRegisterType()) {
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switch (reg.GetRegisterType()) {
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case RegisterType::Output:
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case RegisterType::Output:
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return offsetof(UnitState::Registers, output) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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return offsetof(UnitState, registers.output) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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case RegisterType::Temporary:
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case RegisterType::Temporary:
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return offsetof(UnitState::Registers, temporary) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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return offsetof(UnitState, registers.temporary) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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default:
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default:
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UNREACHABLE();
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UNREACHABLE();
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@ -323,6 +323,23 @@ struct ShaderSetup {
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std::array<Math::Vec4<u8>, 4> i;
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std::array<Math::Vec4<u8>, 4> i;
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} uniforms;
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} uniforms;
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static size_t UniformOffset(RegisterType type, unsigned index) {
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switch (type) {
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case RegisterType::FloatUniform:
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return offsetof(ShaderSetup, uniforms.f) + index*sizeof(Math::Vec4<float24>);
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case RegisterType::BoolUniform:
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return offsetof(ShaderSetup, uniforms.b) + index*sizeof(bool);
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case RegisterType::IntUniform:
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return offsetof(ShaderSetup, uniforms.i) + index*sizeof(Math::Vec4<u8>);
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default:
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UNREACHABLE();
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return 0;
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}
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}
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std::array<u32, 1024> program_code;
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std::array<u32, 1024> program_code;
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std::array<u32, 1024> swizzle_data;
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std::array<u32, 1024> swizzle_data;
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@ -102,7 +102,7 @@ const JitFunction instr_table[64] = {
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// purposes, as documented below:
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// purposes, as documented below:
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/// Pointer to the uniform memory
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/// Pointer to the uniform memory
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static const X64Reg UNIFORMS = R9;
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static const X64Reg SETUP = R9;
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/// The two 32-bit VS address offset registers set by the MOVA instruction
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/// The two 32-bit VS address offset registers set by the MOVA instruction
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static const X64Reg ADDROFFS_REG_0 = R10;
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static const X64Reg ADDROFFS_REG_0 = R10;
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static const X64Reg ADDROFFS_REG_1 = R11;
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static const X64Reg ADDROFFS_REG_1 = R11;
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@ -117,7 +117,7 @@ static const X64Reg COND0 = R13;
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/// Result of the previous CMP instruction for the Y-component comparison
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/// Result of the previous CMP instruction for the Y-component comparison
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static const X64Reg COND1 = R14;
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static const X64Reg COND1 = R14;
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/// Pointer to the UnitState instance for the current VS unit
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/// Pointer to the UnitState instance for the current VS unit
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static const X64Reg REGISTERS = R15;
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static const X64Reg STATE = R15;
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/// SIMD scratch register
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/// SIMD scratch register
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static const X64Reg SCRATCH = XMM0;
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static const X64Reg SCRATCH = XMM0;
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/// Loaded with the first swizzled source register, otherwise can be used as a scratch register
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/// Loaded with the first swizzled source register, otherwise can be used as a scratch register
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@ -136,7 +136,7 @@ static const X64Reg NEGBIT = XMM15;
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// State registers that must not be modified by external functions calls
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// State registers that must not be modified by external functions calls
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// Scratch registers, e.g., SRC1 and SCRATCH, have to be saved on the side if needed
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// Scratch registers, e.g., SRC1 and SCRATCH, have to be saved on the side if needed
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static const BitSet32 persistent_regs = {
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static const BitSet32 persistent_regs = {
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UNIFORMS, REGISTERS, // Pointers to register blocks
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SETUP, STATE, // Pointers to register blocks
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ADDROFFS_REG_0, ADDROFFS_REG_1, LOOPCOUNT_REG, COND0, COND1, // Cached registers
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ADDROFFS_REG_0, ADDROFFS_REG_1, LOOPCOUNT_REG, COND0, COND1, // Cached registers
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ONE+16, NEGBIT+16, // Constants
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ONE+16, NEGBIT+16, // Constants
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};
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};
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@ -177,10 +177,10 @@ void JitShader::Compile_SwizzleSrc(Instruction instr, unsigned src_num, SourceRe
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size_t src_offset;
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size_t src_offset;
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if (src_reg.GetRegisterType() == RegisterType::FloatUniform) {
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if (src_reg.GetRegisterType() == RegisterType::FloatUniform) {
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src_ptr = UNIFORMS;
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src_ptr = SETUP;
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src_offset = src_reg.GetIndex() * sizeof(float24) * 4;
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src_offset = ShaderSetup::UniformOffset(RegisterType::FloatUniform, src_reg.GetIndex());
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} else {
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} else {
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src_ptr = REGISTERS;
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src_ptr = STATE;
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src_offset = UnitState<false>::InputOffset(src_reg);
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src_offset = UnitState<false>::InputOffset(src_reg);
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}
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}
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@ -264,11 +264,11 @@ void JitShader::Compile_DestEnable(Instruction instr,X64Reg src) {
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// If all components are enabled, write the result to the destination register
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// If all components are enabled, write the result to the destination register
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if (swiz.dest_mask == NO_DEST_REG_MASK) {
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if (swiz.dest_mask == NO_DEST_REG_MASK) {
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// Store dest back to memory
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// Store dest back to memory
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MOVAPS(MDisp(REGISTERS, dest_offset_disp), src);
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MOVAPS(MDisp(STATE, dest_offset_disp), src);
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} else {
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} else {
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// Not all components are enabled, so mask the result when storing to the destination register...
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// Not all components are enabled, so mask the result when storing to the destination register...
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MOVAPS(SCRATCH, MDisp(REGISTERS, dest_offset_disp));
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MOVAPS(SCRATCH, MDisp(STATE, dest_offset_disp));
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if (Common::GetCPUCaps().sse4_1) {
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if (Common::GetCPUCaps().sse4_1) {
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u8 mask = ((swiz.dest_mask & 1) << 3) | ((swiz.dest_mask & 8) >> 3) | ((swiz.dest_mask & 2) << 1) | ((swiz.dest_mask & 4) >> 1);
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u8 mask = ((swiz.dest_mask & 1) << 3) | ((swiz.dest_mask & 8) >> 3) | ((swiz.dest_mask & 2) << 1) | ((swiz.dest_mask & 4) >> 1);
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@ -287,7 +287,7 @@ void JitShader::Compile_DestEnable(Instruction instr,X64Reg src) {
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}
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}
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// Store dest back to memory
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// Store dest back to memory
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MOVAPS(MDisp(REGISTERS, dest_offset_disp), SCRATCH);
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MOVAPS(MDisp(STATE, dest_offset_disp), SCRATCH);
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}
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}
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}
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}
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@ -336,8 +336,8 @@ void JitShader::Compile_EvaluateCondition(Instruction instr) {
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}
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}
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void JitShader::Compile_UniformCondition(Instruction instr) {
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void JitShader::Compile_UniformCondition(Instruction instr) {
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int offset = offsetof(decltype(g_state.vs.uniforms), b) + (instr.flow_control.bool_uniform_id * sizeof(bool));
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int offset = ShaderSetup::UniformOffset(RegisterType::BoolUniform, instr.flow_control.bool_uniform_id);
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CMP(sizeof(bool) * 8, MDisp(UNIFORMS, offset), Imm8(0));
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CMP(sizeof(bool) * 8, MDisp(SETUP, offset), Imm8(0));
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}
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}
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BitSet32 JitShader::PersistentCallerSavedRegs() {
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BitSet32 JitShader::PersistentCallerSavedRegs() {
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@ -714,8 +714,8 @@ void JitShader::Compile_LOOP(Instruction instr) {
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looping = true;
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looping = true;
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int offset = offsetof(decltype(g_state.vs.uniforms), i) + (instr.flow_control.int_uniform_id * sizeof(Math::Vec4<u8>));
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int offset = ShaderSetup::UniformOffset(RegisterType::IntUniform, instr.flow_control.int_uniform_id);
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MOV(32, R(LOOPCOUNT), MDisp(UNIFORMS, offset));
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MOV(32, R(LOOPCOUNT), MDisp(SETUP, offset));
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MOV(32, R(LOOPCOUNT_REG), R(LOOPCOUNT));
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MOV(32, R(LOOPCOUNT_REG), R(LOOPCOUNT));
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SHR(32, R(LOOPCOUNT_REG), Imm8(8));
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SHR(32, R(LOOPCOUNT_REG), Imm8(8));
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AND(32, R(LOOPCOUNT_REG), Imm32(0xff)); // Y-component is the start
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AND(32, R(LOOPCOUNT_REG), Imm32(0xff)); // Y-component is the start
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@ -826,8 +826,8 @@ void JitShader::Compile() {
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// The stack pointer is 8 modulo 16 at the entry of a procedure
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// The stack pointer is 8 modulo 16 at the entry of a procedure
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ABI_PushRegistersAndAdjustStack(ABI_ALL_CALLEE_SAVED, 8);
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ABI_PushRegistersAndAdjustStack(ABI_ALL_CALLEE_SAVED, 8);
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MOV(PTRBITS, R(REGISTERS), R(ABI_PARAM1));
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MOV(PTRBITS, R(SETUP), R(ABI_PARAM1));
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MOV(PTRBITS, R(UNIFORMS), ImmPtr(&g_state.vs.uniforms));
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MOV(PTRBITS, R(STATE), R(ABI_PARAM2));
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// Zero address/loop registers
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// Zero address/loop registers
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XOR(64, R(ADDROFFS_REG_0), R(ADDROFFS_REG_0));
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XOR(64, R(ADDROFFS_REG_0), R(ADDROFFS_REG_0));
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@ -845,7 +845,7 @@ void JitShader::Compile() {
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MOVAPS(NEGBIT, MatR(RAX));
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MOVAPS(NEGBIT, MatR(RAX));
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// Jump to start of the shader program
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// Jump to start of the shader program
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JMPptr(R(ABI_PARAM2));
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JMPptr(R(ABI_PARAM3));
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// Compile entire program
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// Compile entire program
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Compile_Block(static_cast<unsigned>(g_state.vs.program_code.size()));
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Compile_Block(static_cast<unsigned>(g_state.vs.program_code.size()));
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@ -36,8 +36,8 @@ class JitShader : public Gen::XCodeBlock {
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public:
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public:
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JitShader();
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JitShader();
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void Run(void* registers, unsigned offset) const {
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void Run(const ShaderSetup& setup, UnitState<false>& state, unsigned offset) const {
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program(registers, code_ptr[offset]);
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program(&setup, &state, code_ptr[offset]);
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}
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}
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void Compile();
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void Compile();
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@ -117,7 +117,7 @@ private:
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/// Branches that need to be fixed up once the entire shader program is compiled
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/// Branches that need to be fixed up once the entire shader program is compiled
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std::vector<std::pair<Gen::FixupBranch, unsigned>> fixup_branches;
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std::vector<std::pair<Gen::FixupBranch, unsigned>> fixup_branches;
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using CompiledShader = void(void* registers, const u8* start_addr);
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using CompiledShader = void(const void* setup, void* state, const u8* start_addr);
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CompiledShader* program = nullptr;
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CompiledShader* program = nullptr;
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};
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};
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