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shader: Implement LEA
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d1edc16ba8
commit
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@ -86,6 +86,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/integer_shift_right.cpp
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frontend/maxwell/translate/impl/integer_short_multiply_add.cpp
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frontend/maxwell/translate/impl/integer_to_integer_conversion.cpp
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frontend/maxwell/translate/impl/load_effective_address.cpp
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frontend/maxwell/translate/impl/load_store_attribute.cpp
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frontend/maxwell/translate/impl/load_store_memory.cpp
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frontend/maxwell/translate/impl/logic_operation.cpp
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@ -132,7 +132,7 @@ void EmitBitCastU64F64(EmitContext& ctx);
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void EmitBitCastF16U16(EmitContext& ctx);
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Id EmitBitCastF32U32(EmitContext& ctx, Id value);
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void EmitBitCastF64U64(EmitContext& ctx);
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void EmitPackUint2x32(EmitContext& ctx);
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Id EmitPackUint2x32(EmitContext& ctx, Id value);
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Id EmitUnpackUint2x32(EmitContext& ctx, Id value);
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Id EmitPackFloat2x16(EmitContext& ctx, Id value);
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Id EmitUnpackFloat2x16(EmitContext& ctx, Id value);
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@ -229,9 +229,11 @@ Id EmitISub32(EmitContext& ctx, Id a, Id b);
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void EmitISub64(EmitContext& ctx);
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Id EmitIMul32(EmitContext& ctx, Id a, Id b);
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Id EmitINeg32(EmitContext& ctx, Id value);
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Id EmitINeg64(EmitContext& ctx, Id value);
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Id EmitIAbs32(EmitContext& ctx, Id value);
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Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
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Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b);
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Id EmitShiftRightLogical64(EmitContext& ctx, Id a, Id b);
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Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b);
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Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b);
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Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b);
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@ -30,8 +30,8 @@ void EmitBitCastF64U64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitPackUint2x32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitPackUint2x32(EmitContext& ctx, Id value) {
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return ctx.OpBitcast(ctx.U64, value);
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}
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Id EmitUnpackUint2x32(EmitContext& ctx, Id value) {
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@ -62,6 +62,10 @@ Id EmitINeg32(EmitContext& ctx, Id value) {
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return ctx.OpSNegate(ctx.U32[1], value);
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}
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Id EmitINeg64(EmitContext& ctx, Id value) {
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return ctx.OpSNegate(ctx.U64, value);
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}
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Id EmitIAbs32(EmitContext& ctx, Id value) {
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return ctx.OpSAbs(ctx.U32[1], value);
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}
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@ -74,6 +78,10 @@ Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpShiftRightLogical(ctx.U32[1], a, b);
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}
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Id EmitShiftRightLogical64(EmitContext& ctx, Id a, Id b) {
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return ctx.OpShiftRightLogical(ctx.U64, a, b);
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}
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Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpShiftRightArithmetic(ctx.U32[1], a, b);
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}
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@ -798,8 +798,15 @@ U32 IREmitter::IMul(const U32& a, const U32& b) {
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return Inst<U32>(Opcode::IMul32, a, b);
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}
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U32 IREmitter::INeg(const U32& value) {
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return Inst<U32>(Opcode::INeg32, value);
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U32U64 IREmitter::INeg(const U32U64& value) {
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switch (value.Type()) {
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case Type::U32:
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return Inst<U32>(Opcode::INeg32, value);
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case Type::U64:
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return Inst<U64>(Opcode::INeg64, value);
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default:
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ThrowInvalidType(value.Type());
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}
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}
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U32 IREmitter::IAbs(const U32& value) {
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@ -810,8 +817,15 @@ U32 IREmitter::ShiftLeftLogical(const U32& base, const U32& shift) {
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return Inst<U32>(Opcode::ShiftLeftLogical32, base, shift);
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}
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U32 IREmitter::ShiftRightLogical(const U32& base, const U32& shift) {
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return Inst<U32>(Opcode::ShiftRightLogical32, base, shift);
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U32U64 IREmitter::ShiftRightLogical(const U32U64& base, const U32& shift) {
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switch (base.Type()) {
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case Type::U32:
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return Inst<U32>(Opcode::ShiftRightLogical32, base, shift);
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case Type::U64:
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return Inst<U64>(Opcode::ShiftRightLogical64, base, shift);
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default:
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ThrowInvalidType(base.Type());
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}
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}
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U32 IREmitter::ShiftRightArithmetic(const U32& base, const U32& shift) {
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@ -148,10 +148,10 @@ public:
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[[nodiscard]] U32U64 IAdd(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32 IMul(const U32& a, const U32& b);
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[[nodiscard]] U32 INeg(const U32& value);
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[[nodiscard]] U32U64 INeg(const U32U64& value);
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[[nodiscard]] U32 IAbs(const U32& value);
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[[nodiscard]] U32 ShiftLeftLogical(const U32& base, const U32& shift);
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[[nodiscard]] U32 ShiftRightLogical(const U32& base, const U32& shift);
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[[nodiscard]] U32U64 ShiftRightLogical(const U32U64& base, const U32& shift);
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[[nodiscard]] U32 ShiftRightArithmetic(const U32& base, const U32& shift);
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[[nodiscard]] U32 BitwiseAnd(const U32& a, const U32& b);
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[[nodiscard]] U32 BitwiseOr(const U32& a, const U32& b);
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@ -233,9 +233,11 @@ OPCODE(ISub32, U32, U32,
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OPCODE(ISub64, U64, U64, U64, )
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OPCODE(IMul32, U32, U32, U32, )
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OPCODE(INeg32, U32, U32, )
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OPCODE(INeg64, U64, U64, )
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OPCODE(IAbs32, U32, U32, )
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OPCODE(ShiftLeftLogical32, U32, U32, U32, )
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OPCODE(ShiftRightLogical32, U32, U32, U32, )
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OPCODE(ShiftRightLogical64, U64, U64, U32, )
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OPCODE(ShiftRightArithmetic32, U32, U32, U32, )
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OPCODE(BitwiseAnd32, U32, U32, U32, )
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OPCODE(BitwiseOr32, U32, U32, U32, )
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@ -0,0 +1,100 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void LEA_hi(TranslatorVisitor& v, u64 insn, const IR::U32& base, IR::U32 offset_hi, u64 scale,
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bool neg, bool x) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> offset_lo_reg;
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BitField<48, 3, IR::Pred> pred;
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} const lea{insn};
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if (x) {
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throw NotImplementedException("LEA.HI X");
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}
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if (lea.pred != IR::Pred::PT) {
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throw NotImplementedException("LEA.LO Pred");
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}
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const IR::U32 offset_lo{v.X(lea.offset_lo_reg)};
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const IR::U64 packed_offset{v.ir.PackUint2x32(v.ir.CompositeConstruct(offset_lo, offset_hi))};
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const IR::U64 offset{neg ? IR::U64{v.ir.INeg(packed_offset)} : packed_offset};
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const s32 hi_scale{32 - static_cast<s32>(scale)};
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const IR::U64 scaled_offset{v.ir.ShiftRightLogical(offset, v.ir.Imm32(hi_scale))};
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const IR::U32 scaled_offset_w0{v.ir.CompositeExtract(v.ir.UnpackUint2x32(scaled_offset), 0)};
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IR::U32 result{v.ir.IAdd(base, scaled_offset_w0)};
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v.X(lea.dest_reg, result);
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}
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void LEA_lo(TranslatorVisitor& v, u64 insn, const IR::U32& base) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> offset_lo_reg;
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BitField<39, 5, u64> scale;
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BitField<45, 1, u64> neg;
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BitField<46, 1, u64> x;
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BitField<48, 3, IR::Pred> pred;
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} const lea{insn};
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if (lea.x != 0) {
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throw NotImplementedException("LEA.LO X");
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}
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if (lea.pred != IR::Pred::PT) {
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throw NotImplementedException("LEA.LO Pred");
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}
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const IR::U32 offset_lo{v.X(lea.offset_lo_reg)};
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const s32 scale{static_cast<s32>(lea.scale)};
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const IR::U32 offset{lea.neg != 0 ? IR::U32{v.ir.INeg(offset_lo)} : offset_lo};
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const IR::U32 scaled_offset{v.ir.ShiftLeftLogical(offset, v.ir.Imm32(scale))};
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IR::U32 result{v.ir.IAdd(base, scaled_offset)};
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v.X(lea.dest_reg, result);
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}
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} // Anonymous namespace
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void TranslatorVisitor::LEA_hi_reg(u64 insn) {
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union {
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u64 insn;
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BitField<28, 5, u64> scale;
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BitField<37, 1, u64> neg;
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BitField<38, 1, u64> x;
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} const lea{insn};
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LEA_hi(*this, insn, GetReg20(insn), GetReg39(insn), lea.scale, lea.neg != 0, lea.x != 0);
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}
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void TranslatorVisitor::LEA_hi_cbuf(u64 insn) {
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union {
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u64 insn;
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BitField<51, 5, u64> scale;
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BitField<56, 1, u64> neg;
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BitField<57, 1, u64> x;
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} const lea{insn};
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LEA_hi(*this, insn, GetCbuf(insn), GetReg39(insn), lea.scale, lea.neg != 0, lea.x != 0);
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}
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void TranslatorVisitor::LEA_lo_reg(u64 insn) {
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LEA_lo(*this, insn, GetReg20(insn));
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}
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void TranslatorVisitor::LEA_lo_cbuf(u64 insn) {
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LEA_lo(*this, insn, GetCbuf(insn));
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}
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void TranslatorVisitor::LEA_lo_imm(u64 insn) {
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LEA_lo(*this, insn, GetImm20(insn));
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}
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} // namespace Shader::Maxwell
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@ -437,26 +437,6 @@ void TranslatorVisitor::LDS(u64) {
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ThrowNotImplemented(Opcode::LDS);
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}
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void TranslatorVisitor::LEA_hi_reg(u64) {
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ThrowNotImplemented(Opcode::LEA_hi_reg);
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}
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void TranslatorVisitor::LEA_hi_cbuf(u64) {
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ThrowNotImplemented(Opcode::LEA_hi_cbuf);
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}
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void TranslatorVisitor::LEA_lo_reg(u64) {
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ThrowNotImplemented(Opcode::LEA_lo_reg);
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}
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void TranslatorVisitor::LEA_lo_cbuf(u64) {
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ThrowNotImplemented(Opcode::LEA_lo_cbuf);
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}
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void TranslatorVisitor::LEA_lo_imm(u64) {
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ThrowNotImplemented(Opcode::LEA_lo_imm);
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}
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void TranslatorVisitor::LEPC(u64) {
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ThrowNotImplemented(Opcode::LEPC);
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}
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