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arm_dyncom_interpreter: slightly change AllocBuffer to be intuitive
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@ -7,6 +7,7 @@
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#include <algorithm>
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#include <cstdio>
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "common/microprofile.h"
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@ -672,19 +673,18 @@ static void LnSWoUB(ScaledRegisterOffset)(ARMul_State* cpu, unsigned int inst, u
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typedef arm_inst * ARM_INST_PTR;
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#define CACHE_BUFFER_SIZE (64 * 1024 * 2000)
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static char inst_buf[CACHE_BUFFER_SIZE];
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static int top = 0;
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static inline void *AllocBuffer(unsigned int size) {
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int start = top;
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top += size;
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if (top > CACHE_BUFFER_SIZE) {
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LOG_ERROR(Core_ARM11, "inst_buf is full");
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CITRA_IGNORE_EXIT(-1);
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}
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return (void *)&inst_buf[start];
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#define TRANS_CACHE_SIZE (64 * 1024 * 2000)
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static char trans_cache_buf[TRANS_CACHE_SIZE];
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static size_t trans_cache_buf_top = 0;
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static void* AllocBuffer(size_t size) {
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size_t start = trans_cache_buf_top;
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trans_cache_buf_top += size;
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ASSERT_MSG(trans_cache_buf_top <= TRANS_CACHE_SIZE, "Translation cache is full!");
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return static_cast<void*>(&trans_cache_buf[start]);
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}
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static shtop_fp_t GetShifterOp(unsigned int inst) {
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if (BIT(inst, 25)) {
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return DPO(Immediate);
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@ -870,7 +870,7 @@ static int InterpreterTranslateBlock(ARMul_State* cpu, int& bb_start, u32 addr)
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ARM_INST_PTR inst_base = nullptr;
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TransExtData ret = TransExtData::NON_BRANCH;
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int size = 0; // instruction size of basic block
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bb_start = top;
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bb_start = trans_cache_buf_top;
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u32 phys_addr = addr;
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u32 pc_start = cpu->Reg[15];
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@ -897,7 +897,7 @@ static int InterpreterTranslateSingle(ARMul_State* cpu, int& bb_start, u32 addr)
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MICROPROFILE_SCOPE(DynCom_Decode);
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ARM_INST_PTR inst_base = nullptr;
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bb_start = top;
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bb_start = trans_cache_buf_top;
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u32 phys_addr = addr;
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u32 pc_start = cpu->Reg[15];
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@ -951,7 +951,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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#define SHIFTER_OPERAND inst_cream->shtop_func(cpu, inst_cream->shifter_operand)
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#define FETCH_INST if (inst_base->br != TransExtData::NON_BRANCH) goto DISPATCH; \
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inst_base = (arm_inst *)&inst_buf[ptr]
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inst_base = (arm_inst *)&trans_cache_buf[ptr]
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#define INC_PC(l) ptr += sizeof(arm_inst) + l
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#define INC_PC_STUB ptr += sizeof(arm_inst)
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@ -1274,7 +1274,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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breakpoint_data = GDBStub::GetNextBreakpointFromAddress(cpu->Reg[15], GDBStub::BreakpointType::Execute);
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}
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inst_base = (arm_inst *)&inst_buf[ptr];
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inst_base = (arm_inst *)&trans_cache_buf[ptr];
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GOTO_NEXT_INST;
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}
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ADC_INST:
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