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Merge pull request #1106 from Subv/multiple_rendertargets
Shaders: Write all the enabled color outputs when a fragment shader exits.
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commit
5aaee2ff8d
@ -26,6 +26,7 @@ using Tegra::Shader::Sampler;
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using Tegra::Shader::SubOp;
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constexpr u32 PROGRAM_END = MAX_PROGRAM_CODE_LENGTH;
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constexpr u32 PROGRAM_HEADER_SIZE = 0x50;
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class DecompileFail : public std::runtime_error {
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public:
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@ -621,6 +622,23 @@ public:
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}
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private:
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// Shader program header for a Fragment Shader.
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struct FragmentHeader {
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INSERT_PADDING_WORDS(5);
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INSERT_PADDING_WORDS(13);
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u32 enabled_color_outputs;
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union {
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BitField<0, 1, u32> writes_samplemask;
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BitField<1, 1, u32> writes_depth;
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};
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bool IsColorComponentOutputEnabled(u32 render_target, u32 component) const {
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u32 bit = render_target * 4 + component;
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return enabled_color_outputs & (1 << bit);
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}
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};
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static_assert(sizeof(FragmentHeader) == PROGRAM_HEADER_SIZE, "FragmentHeader size is wrong");
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/// Gets the Subroutine object corresponding to the specified address.
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const Subroutine& GetSubroutine(u32 begin, u32 end) const {
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auto iter = subroutines.find(Subroutine{begin, end, suffix});
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@ -894,6 +912,31 @@ private:
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shader.AddLine('}');
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}
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/// Writes the output values from a fragment shader to the corresponding GLSL output variables.
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void EmitFragmentOutputsWrite() {
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ASSERT(stage == Maxwell3D::Regs::ShaderStage::Fragment);
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FragmentHeader header;
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std::memcpy(&header, program_code.data(), PROGRAM_HEADER_SIZE);
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ASSERT_MSG(header.writes_depth == 0, "Depth write is unimplemented");
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ASSERT_MSG(header.writes_samplemask == 0, "Samplemask write is unimplemented");
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// Write the color outputs using the data in the shader registers, disabled
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// rendertargets/components are skipped in the register assignment.
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u32 current_reg = 0;
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for (u32 render_target = 0; render_target < Maxwell3D::Regs::NumRenderTargets;
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++render_target) {
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// TODO(Subv): Figure out how dual-source blending is configured in the Switch.
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for (u32 component = 0; component < 4; ++component) {
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if (header.IsColorComponentOutputEnabled(render_target, component)) {
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shader.AddLine(fmt::format("color[{}][{}] = {};", render_target, component,
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regs.GetRegisterAsFloat(current_reg)));
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++current_reg;
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}
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}
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}
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}
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/**
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* Compiles a single instruction from Tegra to GLSL.
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* @param offset the offset of the Tegra shader instruction.
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@ -1969,12 +2012,8 @@ private:
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default: {
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switch (opcode->GetId()) {
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case OpCode::Id::EXIT: {
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// Final color output is currently hardcoded to GPR0-3 for fragment shaders
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment) {
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shader.AddLine("color.r = " + regs.GetRegisterAsFloat(0) + ';');
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shader.AddLine("color.g = " + regs.GetRegisterAsFloat(1) + ';');
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shader.AddLine("color.b = " + regs.GetRegisterAsFloat(2) + ';');
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shader.AddLine("color.a = " + regs.GetRegisterAsFloat(3) + ';');
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EmitFragmentOutputsWrite();
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}
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switch (instr.flow.cond) {
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@ -87,7 +87,7 @@ ProgramResult GenerateFragmentShader(const ShaderSetup& setup, const MaxwellFSCo
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.get_value_or({});
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out += R"(
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in vec4 position;
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out vec4 color;
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layout(location = 0) out vec4 color[8];
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layout (std140) uniform fs_config {
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vec4 viewport_flip;
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