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shader_decode: Implement TEXS.F16
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@ -219,8 +219,7 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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if (instr.texs.fp32_flag) {
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WriteTexsInstructionFloat(bb, instr, texture);
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} else {
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UNIMPLEMENTED();
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// WriteTexsInstructionHalfFloat(bb, instr, texture);
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WriteTexsInstructionHalfFloat(bb, instr, texture);
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}
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break;
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}
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@ -416,39 +415,52 @@ const Sampler& ShaderIR::GetSampler(const Tegra::Shader::Sampler& sampler, Textu
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return *used_samplers.emplace(entry).first;
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}
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void ShaderIR::WriteTexsInstructionFloat(BasicBlock& bb, Tegra::Shader::Instruction instr,
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Node texture) {
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void ShaderIR::WriteTexsInstructionFloat(BasicBlock& bb, Instruction instr, Node texture) {
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// TEXS has two destination registers and a swizzle. The first two elements in the swizzle
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// go into gpr0+0 and gpr0+1, and the rest goes into gpr28+0 and gpr28+1
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MetaComponents meta;
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std::array<Node, 4> dest;
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std::size_t written_components = 0;
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for (u32 component = 0; component < 4; ++component) {
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if (!instr.texs.IsComponentEnabled(component)) {
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continue;
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}
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meta.components_map[written_components] = static_cast<u32>(component);
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meta.components_map[meta.count] = component;
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if (written_components < 2) {
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if (meta.count < 2) {
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// Write the first two swizzle components to gpr0 and gpr0+1
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dest[written_components] = GetRegister(instr.gpr0.Value() + written_components % 2);
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dest[meta.count] = GetRegister(instr.gpr0.Value() + meta.count % 2);
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} else {
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ASSERT(instr.texs.HasTwoDestinations());
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// Write the rest of the swizzle components to gpr28 and gpr28+1
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dest[written_components] = GetRegister(instr.gpr28.Value() + written_components % 2);
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dest[meta.count] = GetRegister(instr.gpr28.Value() + meta.count % 2);
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}
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++written_components;
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++meta.count;
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}
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std::generate(dest.begin() + written_components, dest.end(), [&]() { return GetRegister(RZ); });
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std::generate(dest.begin() + meta.count, dest.end(), [&]() { return GetRegister(RZ); });
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bb.push_back(Operation(OperationCode::AssignComposite, meta, texture, dest[0], dest[1], dest[2],
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dest[3]));
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}
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void ShaderIR::WriteTexsInstructionHalfFloat(BasicBlock& bb, Instruction instr, Node texture) {
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// TEXS.F16 destionation registers are packed in two registers in pairs (just like any half
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// float instruction).
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MetaComponents meta;
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for (u32 component = 0; component < 4; ++component) {
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if (!instr.texs.IsComponentEnabled(component))
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continue;
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meta.components_map[meta.count++] = component;
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}
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if (meta.count == 0)
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return;
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bb.push_back(Operation(OperationCode::AssignCompositeHalf, meta, texture,
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GetRegister(instr.gpr0), GetRegister(instr.gpr28)));
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}
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Node ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
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TextureProcessMode process_mode, bool depth_compare, bool is_array,
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std::size_t array_offset, std::size_t bias_offset,
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@ -785,6 +785,31 @@ private:
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return {};
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}
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std::string AssignCompositeHalf(Operation operation) {
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const auto& meta = std::get<MetaComponents>(operation.GetMeta());
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const std::string composite = code.GenerateTemporal();
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code.AddLine("vec4 " + composite + " = " + Visit(operation[0]) + ';');
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const auto ReadComponent = [&](u32 component) {
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if (component < meta.count) {
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return composite + '[' + std::to_string(meta.GetSourceComponent(component)) + ']';
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}
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return std::string("0");
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};
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const auto dst1 = std::get<GprNode>(*operation[1]).GetIndex();
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const std::string src1 = "vec2(" + ReadComponent(0) + ", " + ReadComponent(1) + ')';
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code.AddLine(GetRegister(dst1) + " = utof(packHalf2x16(" + src1 + "))");
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if (meta.count > 2) {
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const auto dst2 = std::get<GprNode>(*operation[2]).GetIndex();
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const std::string src2 = "vec2(" + ReadComponent(2) + ", " + ReadComponent(3) + ')';
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code.AddLine(GetRegister(dst2) + " = utof(packHalf2x16(" + src2 + "))");
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}
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return {};
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}
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std::string Composite(Operation operation) {
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std::string value = "vec4(";
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for (std::size_t i = 0; i < 4; ++i) {
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@ -1302,6 +1327,7 @@ private:
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static constexpr OperationDecompilersArray operation_decompilers = {
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&GLSLDecompiler::Assign,
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&GLSLDecompiler::AssignComposite,
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&GLSLDecompiler::AssignCompositeHalf,
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&GLSLDecompiler::Composite,
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&GLSLDecompiler::Select,
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@ -44,8 +44,9 @@ constexpr u32 MAX_PROGRAM_LENGTH = 0x1000;
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constexpr u32 RZ = 0xff;
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enum class OperationCode {
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Assign, /// (float& dest, float src) -> void
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AssignComposite, /// (MetaComponents, float4 src, float&[4] dst) -> void
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Assign, /// (float& dest, float src) -> void
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AssignComposite, /// (MetaComponents, float4 src, float&[4] dst) -> void
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AssignCompositeHalf, /// (MetaComponents, float4 src, float&[2] dst) -> void
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Composite, /// (float[4] values) -> float4
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Select, /// (MetaArithmetic, bool pred, float a, float b) -> float
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@ -279,6 +280,7 @@ struct MetaTexture {
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struct MetaComponents {
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std::array<u32, 4> components_map{};
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u32 count{};
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u32 GetSourceComponent(u32 dest_index) const {
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return components_map[dest_index];
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@ -692,6 +694,8 @@ private:
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Tegra::Shader::TextureType type, bool is_array, bool is_shadow);
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void WriteTexsInstructionFloat(BasicBlock& bb, Tegra::Shader::Instruction instr, Node texture);
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void WriteTexsInstructionHalfFloat(BasicBlock& bb, Tegra::Shader::Instruction instr,
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Node texture);
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Node GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
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