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vk_compute_pass: Fix compute passes
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5ed68e83db
commit
5b3c6d59c2
@ -206,27 +206,23 @@ VKComputePass::VKComputePass(const Device& device, VKDescriptorPool& descriptor_
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.codeSize = static_cast<u32>(code.size_bytes()),
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.pCode = code.data(),
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});
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/*
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FIXME
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pipeline = device.GetLogical().CreateComputePipeline({
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.stage =
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{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = *module,
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.pName = "main",
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.pSpecializationInfo = nullptr,
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},
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.stage{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = *module,
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.pName = "main",
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.pSpecializationInfo = nullptr,
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},
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.layout = *layout,
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.basePipelineHandle = nullptr,
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.basePipelineIndex = 0,
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});
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*/
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}
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VKComputePass::~VKComputePass() = default;
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@ -262,8 +258,7 @@ std::pair<VkBuffer, VkDeviceSize> Uint8Pass::Assemble(u32 num_vertices, VkBuffer
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const VkDescriptorSet set = CommitDescriptorSet(update_descriptor_queue);
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scheduler.RequestOutsideRenderPassOperationContext();
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scheduler.Record([layout = *layout, pipeline = *pipeline, buffer = staging.buffer, set,
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num_vertices](vk::CommandBuffer cmdbuf) {
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scheduler.Record([this, buffer = staging.buffer, set, num_vertices](vk::CommandBuffer cmdbuf) {
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static constexpr u32 DISPATCH_SIZE = 1024;
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static constexpr VkMemoryBarrier WRITE_BARRIER{
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.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
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@ -271,8 +266,8 @@ std::pair<VkBuffer, VkDeviceSize> Uint8Pass::Assemble(u32 num_vertices, VkBuffer
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.srcAccessMask = VK_ACCESS_SHADER_WRITE_BIT,
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.dstAccessMask = VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT,
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};
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cmdbuf.BindPipeline(VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
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cmdbuf.BindDescriptorSets(VK_PIPELINE_BIND_POINT_COMPUTE, layout, 0, set, {});
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cmdbuf.BindPipeline(VK_PIPELINE_BIND_POINT_COMPUTE, *pipeline);
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cmdbuf.BindDescriptorSets(VK_PIPELINE_BIND_POINT_COMPUTE, *layout, 0, set, {});
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cmdbuf.Dispatch(Common::DivCeil(num_vertices, DISPATCH_SIZE), 1, 1);
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cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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VK_PIPELINE_STAGE_VERTEX_INPUT_BIT, 0, WRITE_BARRIER);
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@ -319,8 +314,8 @@ std::pair<VkBuffer, VkDeviceSize> QuadIndexedPass::Assemble(
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const VkDescriptorSet set = CommitDescriptorSet(update_descriptor_queue);
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scheduler.RequestOutsideRenderPassOperationContext();
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scheduler.Record([layout = *layout, pipeline = *pipeline, buffer = staging.buffer, set,
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num_tri_vertices, base_vertex, index_shift](vk::CommandBuffer cmdbuf) {
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scheduler.Record([this, buffer = staging.buffer, set, num_tri_vertices, base_vertex,
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index_shift](vk::CommandBuffer cmdbuf) {
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static constexpr u32 DISPATCH_SIZE = 1024;
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static constexpr VkMemoryBarrier WRITE_BARRIER{
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.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
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@ -329,9 +324,9 @@ std::pair<VkBuffer, VkDeviceSize> QuadIndexedPass::Assemble(
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.dstAccessMask = VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT,
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};
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const std::array push_constants = {base_vertex, index_shift};
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cmdbuf.BindPipeline(VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
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cmdbuf.BindDescriptorSets(VK_PIPELINE_BIND_POINT_COMPUTE, layout, 0, set, {});
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cmdbuf.PushConstants(layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants),
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cmdbuf.BindPipeline(VK_PIPELINE_BIND_POINT_COMPUTE, *pipeline);
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cmdbuf.BindDescriptorSets(VK_PIPELINE_BIND_POINT_COMPUTE, *layout, 0, set, {});
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cmdbuf.PushConstants(*layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants),
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&push_constants);
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cmdbuf.Dispatch(Common::DivCeil(num_tri_vertices, DISPATCH_SIZE), 1, 1);
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cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,
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@ -189,6 +189,8 @@ void GraphicsPipeline::Configure(bool is_indexed) {
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buffer_cache.BindHostGeometryBuffers(is_indexed);
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update_descriptor_queue.Acquire();
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size_t index{};
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for (size_t stage = 0; stage < Maxwell::MaxShaderStage; ++stage) {
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buffer_cache.BindHostStageBuffers(stage);
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@ -172,7 +172,6 @@ void RasterizerVulkan::Draw(bool is_indexed, bool is_instanced) {
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if (!pipeline) {
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return;
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}
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update_descriptor_queue.Acquire();
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std::scoped_lock lock{buffer_cache.mutex, texture_cache.mutex};
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pipeline->Configure(is_indexed);
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