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https://github.com/yuzu-emu/yuzu.git
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shader_ir: Rename Get/SetTemporal to Get/SetTemporary
This is more accurate in terms of describing what the functions are actually doing. Temporal relates to time, not the setting of a temporary itself.
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44d87ff641
commit
60926ac16b
@ -95,10 +95,10 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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const Node op_b =
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GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.GetOffset() + 4, index);
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SetTemporal(bb, 0, op_a);
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SetTemporal(bb, 1, op_b);
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SetRegister(bb, instr.gpr0, GetTemporal(0));
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SetRegister(bb, instr.gpr0.Value() + 1, GetTemporal(1));
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SetTemporary(bb, 0, op_a);
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SetTemporary(bb, 1, op_b);
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SetRegister(bb, instr.gpr0, GetTemporary(0));
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SetRegister(bb, instr.gpr0.Value() + 1, GetTemporary(1));
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break;
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}
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default:
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@ -136,9 +136,9 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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}
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}();
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for (u32 i = 0; i < count; ++i)
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SetTemporal(bb, i, GetLmem(i * 4));
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SetTemporary(bb, i, GetLmem(i * 4));
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for (u32 i = 0; i < count; ++i)
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i));
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
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break;
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}
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default:
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@ -172,10 +172,10 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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Operation(OperationCode::UAdd, NO_PRECISE, real_address_base, it_offset);
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const Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor);
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SetTemporal(bb, i, gmem);
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SetTemporary(bb, i, gmem);
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}
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for (u32 i = 0; i < count; ++i) {
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i));
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
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}
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break;
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}
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@ -253,11 +253,11 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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TrackAndGetGlobalMemory(bb, instr, true);
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// Encode in temporary registers like this: real_base_address, {registers_to_be_written...}
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SetTemporal(bb, 0, real_address_base);
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SetTemporary(bb, 0, real_address_base);
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const u32 count = GetUniformTypeElementsCount(type);
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for (u32 i = 0; i < count; ++i) {
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SetTemporal(bb, i + 1, GetRegister(instr.gpr0.Value() + i));
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SetTemporary(bb, i + 1, GetRegister(instr.gpr0.Value() + i));
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}
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for (u32 i = 0; i < count; ++i) {
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const Node it_offset = Immediate(i * 4);
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@ -265,7 +265,7 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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Operation(OperationCode::UAdd, NO_PRECISE, real_address_base, it_offset);
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const Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor);
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bb.push_back(Operation(OperationCode::Assign, gmem, GetTemporal(i + 1)));
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bb.push_back(Operation(OperationCode::Assign, gmem, GetTemporary(i + 1)));
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}
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break;
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}
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@ -181,10 +181,10 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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const Node value =
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Operation(OperationCode::TextureQueryDimensions, meta,
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GetRegister(instr.gpr8.Value() + (is_bindless ? 1 : 0)));
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SetTemporal(bb, indexer++, value);
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SetTemporary(bb, indexer++, value);
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}
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for (u32 i = 0; i < indexer; ++i) {
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i));
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
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}
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break;
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}
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@ -238,10 +238,10 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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auto params = coords;
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MetaTexture meta{sampler, {}, {}, {}, {}, {}, {}, element};
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const Node value = Operation(OperationCode::TextureQueryLod, meta, std::move(params));
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SetTemporal(bb, indexer++, value);
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SetTemporary(bb, indexer++, value);
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}
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for (u32 i = 0; i < indexer; ++i) {
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i));
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
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}
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break;
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}
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@ -336,11 +336,11 @@ void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const
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// Skip disabled components
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continue;
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}
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SetTemporal(bb, dest_elem++, components[elem]);
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SetTemporary(bb, dest_elem++, components[elem]);
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}
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// After writing values in temporals, move them to the real registers
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for (u32 i = 0; i < dest_elem; ++i) {
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i));
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
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}
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}
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@ -353,17 +353,17 @@ void ShaderIR::WriteTexsInstructionFloat(NodeBlock& bb, Instruction instr,
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for (u32 component = 0; component < 4; ++component) {
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if (!instr.texs.IsComponentEnabled(component))
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continue;
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SetTemporal(bb, dest_elem++, components[component]);
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SetTemporary(bb, dest_elem++, components[component]);
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}
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for (u32 i = 0; i < dest_elem; ++i) {
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if (i < 2) {
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// Write the first two swizzle components to gpr0 and gpr0+1
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SetRegister(bb, instr.gpr0.Value() + i % 2, GetTemporal(i));
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SetRegister(bb, instr.gpr0.Value() + i % 2, GetTemporary(i));
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} else {
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ASSERT(instr.texs.HasTwoDestinations());
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// Write the rest of the swizzle components to gpr28 and gpr28+1
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SetRegister(bb, instr.gpr28.Value() + i % 2, GetTemporal(i));
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SetRegister(bb, instr.gpr28.Value() + i % 2, GetTemporary(i));
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}
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}
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}
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@ -391,11 +391,11 @@ void ShaderIR::WriteTexsInstructionHalfFloat(NodeBlock& bb, Instruction instr,
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return;
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}
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SetTemporal(bb, 0, first_value);
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SetTemporal(bb, 1, Operation(OperationCode::HPack2, values[2], values[3]));
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SetTemporary(bb, 0, first_value);
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SetTemporary(bb, 1, Operation(OperationCode::HPack2, values[2], values[3]));
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SetRegister(bb, instr.gpr0, GetTemporal(0));
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SetRegister(bb, instr.gpr28, GetTemporal(1));
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SetRegister(bb, instr.gpr0, GetTemporary(0));
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SetRegister(bb, instr.gpr28, GetTemporary(1));
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}
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Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
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@ -73,8 +73,8 @@ u32 ShaderIR::DecodeXmad(NodeBlock& bb, u32 pc) {
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if (is_psl) {
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product = Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, product, Immediate(16));
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}
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SetTemporal(bb, 0, product);
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product = GetTemporal(0);
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SetTemporary(bb, 0, product);
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product = GetTemporary(0);
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const Node original_c = op_c;
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const Tegra::Shader::XmadMode set_mode = mode; // Workaround to clang compile error
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@ -98,13 +98,13 @@ u32 ShaderIR::DecodeXmad(NodeBlock& bb, u32 pc) {
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}
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}();
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SetTemporal(bb, 1, op_c);
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op_c = GetTemporal(1);
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SetTemporary(bb, 1, op_c);
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op_c = GetTemporary(1);
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// TODO(Rodrigo): Use an appropiate sign for this operation
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Node sum = Operation(OperationCode::IAdd, product, op_c);
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SetTemporal(bb, 2, sum);
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sum = GetTemporal(2);
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SetTemporary(bb, 2, sum);
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sum = GetTemporary(2);
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if (is_merge) {
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const Node a = BitfieldExtract(sum, 0, 16);
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const Node b =
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@ -137,7 +137,7 @@ Node ShaderIR::GetLocalMemory(Node address) {
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return MakeNode<LmemNode>(address);
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}
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Node ShaderIR::GetTemporal(u32 id) {
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Node ShaderIR::GetTemporary(u32 id) {
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return GetRegister(Register::ZeroIndex + 1 + id);
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}
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@ -373,7 +373,7 @@ void ShaderIR::SetLocalMemory(NodeBlock& bb, Node address, Node value) {
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bb.push_back(Operation(OperationCode::Assign, GetLocalMemory(address), value));
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}
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void ShaderIR::SetTemporal(NodeBlock& bb, u32 id, Node value) {
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void ShaderIR::SetTemporary(NodeBlock& bb, u32 id, Node value) {
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SetRegister(bb, Register::ZeroIndex + 1 + id, value);
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}
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@ -207,8 +207,8 @@ private:
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Node GetInternalFlag(InternalFlag flag, bool negated = false);
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/// Generates a node representing a local memory address
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Node GetLocalMemory(Node address);
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/// Generates a temporal, internally it uses a post-RZ register
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Node GetTemporal(u32 id);
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/// Generates a temporary, internally it uses a post-RZ register
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Node GetTemporary(u32 id);
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/// Sets a register. src value must be a number-evaluated node.
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void SetRegister(NodeBlock& bb, Tegra::Shader::Register dest, Node src);
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@ -218,8 +218,8 @@ private:
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void SetInternalFlag(NodeBlock& bb, InternalFlag flag, Node value);
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/// Sets a local memory address. address and value must be a number-evaluated node
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void SetLocalMemory(NodeBlock& bb, Node address, Node value);
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/// Sets a temporal. Internally it uses a post-RZ register
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void SetTemporal(NodeBlock& bb, u32 id, Node value);
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/// Sets a temporary. Internally it uses a post-RZ register
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void SetTemporary(NodeBlock& bb, u32 id, Node value);
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/// Sets internal flags from a float
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void SetInternalFlagsFromFloat(NodeBlock& bb, Node value, bool sets_cc = true);
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