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shader_ir/memory: Implement patch stores
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@ -98,10 +98,11 @@ union Attribute {
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BitField<20, 10, u64> immediate;
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BitField<22, 2, u64> element;
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BitField<24, 6, Index> index;
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BitField<31, 1, u64> patch;
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BitField<47, 3, AttributeSize> size;
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bool IsPhysical() const {
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return element == 0 && static_cast<u64>(index.Value()) == 0;
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return patch == 0 && element == 0 && static_cast<u64>(index.Value()) == 0;
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}
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} fmt20;
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@ -21,6 +21,7 @@ using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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namespace {
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u32 GetUniformTypeElementsCount(Tegra::Shader::UniformType uniform_type) {
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switch (uniform_type) {
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case Tegra::Shader::UniformType::Single:
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@ -35,6 +36,7 @@ u32 GetUniformTypeElementsCount(Tegra::Shader::UniformType uniform_type) {
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return 1;
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}
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}
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} // Anonymous namespace
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u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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@ -196,28 +198,28 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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UNIMPLEMENTED_IF_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) != 0,
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"Unaligned attribute loads are not supported");
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u64 next_element = instr.attribute.fmt20.element;
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auto next_index = static_cast<u64>(instr.attribute.fmt20.index.Value());
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u64 element = instr.attribute.fmt20.element;
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auto index = static_cast<u64>(instr.attribute.fmt20.index.Value());
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const auto StoreNextElement = [&](u32 reg_offset) {
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const auto dest = GetOutputAttribute(static_cast<Attribute::Index>(next_index),
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next_element, GetRegister(instr.gpr39));
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const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1;
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for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) {
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Node dest;
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if (instr.attribute.fmt20.patch) {
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const u32 offset = static_cast<u32>(index) * 4 + static_cast<u32>(element);
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dest = MakeNode<PatchNode>(offset);
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} else {
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dest = GetOutputAttribute(static_cast<Attribute::Index>(index), element,
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GetRegister(instr.gpr39));
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}
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const auto src = GetRegister(instr.gpr0.Value() + reg_offset);
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bb.push_back(Operation(OperationCode::Assign, dest, src));
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// Load the next attribute element into the following register. If the element
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// to load goes beyond the vec4 size, load the first element of the next
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// attribute.
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next_element = (next_element + 1) % 4;
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next_index = next_index + (next_element == 0 ? 1 : 0);
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};
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const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1;
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for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) {
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StoreNextElement(reg_offset);
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// Load the next attribute element into the following register. If the element to load
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// goes beyond the vec4 size, load the first element of the next attribute.
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element = (element + 1) % 4;
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index = index + (element == 0 ? 1 : 0);
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}
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break;
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}
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case OpCode::Id::ST_L:
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@ -213,13 +213,14 @@ class PredicateNode;
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class AbufNode;
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class CbufNode;
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class LmemNode;
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class PatchNode;
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class SmemNode;
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class GmemNode;
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class CommentNode;
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using NodeData =
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std::variant<OperationNode, ConditionalNode, GprNode, ImmediateNode, InternalFlagNode,
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PredicateNode, AbufNode, CbufNode, LmemNode, SmemNode, GmemNode, CommentNode>;
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using NodeData = std::variant<OperationNode, ConditionalNode, GprNode, ImmediateNode,
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InternalFlagNode, PredicateNode, AbufNode, PatchNode, CbufNode,
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LmemNode, SmemNode, GmemNode, CommentNode>;
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using Node = std::shared_ptr<NodeData>;
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using Node4 = std::array<Node, 4>;
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using NodeBlock = std::vector<Node>;
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@ -542,6 +543,19 @@ private:
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u32 element{};
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};
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/// Patch memory (used to communicate tessellation stages).
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class PatchNode final {
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public:
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explicit PatchNode(u32 offset) : offset{offset} {}
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u32 GetOffset() const {
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return offset;
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}
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private:
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u32 offset{};
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};
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/// Constant buffer node, usually mapped to uniform buffers in GLSL
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class CbufNode final {
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public:
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@ -7,6 +7,7 @@
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#include <variant>
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#include "common/common_types.h"
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#include "video_core/shader/node.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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