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Merge pull request #8098 from merryhime/ic-ivau
dynarmic: Invalidate CPU cache on all cores
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commit
642913b0d1
2
externals/dynarmic
vendored
2
externals/dynarmic
vendored
@ -1 +1 @@
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Subproject commit e1a266b9299be81cc0318c7e25b00388c342704f
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Subproject commit af2d50288fc537201014c4230bb55ab9018a7438
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@ -93,17 +93,19 @@ public:
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static constexpr u64 ICACHE_LINE_SIZE = 64;
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static constexpr u64 ICACHE_LINE_SIZE = 64;
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const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
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const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
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parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
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parent.system.InvalidateCpuInstructionCacheRange(cache_line_start, ICACHE_LINE_SIZE);
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break;
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break;
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}
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}
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
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parent.ClearInstructionCache();
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parent.system.InvalidateCpuInstructionCaches();
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break;
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break;
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
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default:
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default:
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LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
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LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
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break;
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break;
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}
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}
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parent.jit->HaltExecution();
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}
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}
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
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