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core: dynarmic: Add CP15 from Citra.
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@ -597,6 +597,8 @@ if (ARCHITECTURE_x86_64)
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target_sources(core PRIVATE
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arm/dynarmic/arm_dynarmic.cpp
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arm/dynarmic/arm_dynarmic.h
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arm/dynarmic/arm_dynarmic_cp15.cpp
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arm/dynarmic/arm_dynarmic_cp15.h
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)
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target_link_libraries(core PRIVATE dynarmic)
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endif()
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80
src/core/arm/dynarmic/arm_dynarmic_cp15.cpp
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80
src/core/arm/dynarmic/arm_dynarmic_cp15.cpp
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// Copyright 2017 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "core/arm/dynarmic/arm_dynarmic_cp15.h"
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using Callback = Dynarmic::A32::Coprocessor::Callback;
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using CallbackOrAccessOneWord = Dynarmic::A32::Coprocessor::CallbackOrAccessOneWord;
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using CallbackOrAccessTwoWords = Dynarmic::A32::Coprocessor::CallbackOrAccessTwoWords;
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std::optional<Callback> DynarmicCP15::CompileInternalOperation(bool two, unsigned opc1,
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CoprocReg CRd, CoprocReg CRn,
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CoprocReg CRm, unsigned opc2) {
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return {};
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}
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CallbackOrAccessOneWord DynarmicCP15::CompileSendOneWord(bool two, unsigned opc1, CoprocReg CRn,
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CoprocReg CRm, unsigned opc2) {
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// TODO(merry): Privileged CP15 registers
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if (!two && CRn == CoprocReg::C7 && opc1 == 0 && CRm == CoprocReg::C5 && opc2 == 4) {
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// This is a dummy write, we ignore the value written here.
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return &CP15[static_cast<std::size_t>(CP15Register::CP15_FLUSH_PREFETCH_BUFFER)];
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}
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if (!two && CRn == CoprocReg::C7 && opc1 == 0 && CRm == CoprocReg::C10) {
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switch (opc2) {
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case 4:
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// This is a dummy write, we ignore the value written here.
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return &CP15[static_cast<std::size_t>(CP15Register::CP15_DATA_SYNC_BARRIER)];
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case 5:
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// This is a dummy write, we ignore the value written here.
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return &CP15[static_cast<std::size_t>(CP15Register::CP15_DATA_MEMORY_BARRIER)];
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default:
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return {};
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}
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}
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if (!two && CRn == CoprocReg::C13 && opc1 == 0 && CRm == CoprocReg::C0 && opc2 == 2) {
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return &CP15[static_cast<std::size_t>(CP15Register::CP15_THREAD_UPRW)];
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}
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return {};
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}
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CallbackOrAccessTwoWords DynarmicCP15::CompileSendTwoWords(bool two, unsigned opc, CoprocReg CRm) {
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return {};
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}
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CallbackOrAccessOneWord DynarmicCP15::CompileGetOneWord(bool two, unsigned opc1, CoprocReg CRn,
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CoprocReg CRm, unsigned opc2) {
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// TODO(merry): Privileged CP15 registers
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if (!two && CRn == CoprocReg::C13 && opc1 == 0 && CRm == CoprocReg::C0) {
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switch (opc2) {
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case 2:
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return &CP15[static_cast<std::size_t>(CP15Register::CP15_THREAD_UPRW)];
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case 3:
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return &CP15[static_cast<std::size_t>(CP15Register::CP15_THREAD_URO)];
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default:
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return {};
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}
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}
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return {};
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}
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CallbackOrAccessTwoWords DynarmicCP15::CompileGetTwoWords(bool two, unsigned opc, CoprocReg CRm) {
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return {};
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}
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std::optional<Callback> DynarmicCP15::CompileLoadWords(bool two, bool long_transfer, CoprocReg CRd,
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std::optional<u8> option) {
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return {};
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}
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std::optional<Callback> DynarmicCP15::CompileStoreWords(bool two, bool long_transfer, CoprocReg CRd,
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std::optional<u8> option) {
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return {};
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}
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152
src/core/arm/dynarmic/arm_dynarmic_cp15.h
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152
src/core/arm/dynarmic/arm_dynarmic_cp15.h
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@ -0,0 +1,152 @@
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// Copyright 2017 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <memory>
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#include <optional>
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#include <dynarmic/A32/coprocessor.h>
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#include "common/common_types.h"
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enum class CP15Register {
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// c0 - Information registers
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CP15_MAIN_ID,
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CP15_CACHE_TYPE,
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CP15_TCM_STATUS,
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CP15_TLB_TYPE,
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CP15_CPU_ID,
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CP15_PROCESSOR_FEATURE_0,
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CP15_PROCESSOR_FEATURE_1,
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CP15_DEBUG_FEATURE_0,
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CP15_AUXILIARY_FEATURE_0,
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CP15_MEMORY_MODEL_FEATURE_0,
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CP15_MEMORY_MODEL_FEATURE_1,
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CP15_MEMORY_MODEL_FEATURE_2,
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CP15_MEMORY_MODEL_FEATURE_3,
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CP15_ISA_FEATURE_0,
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CP15_ISA_FEATURE_1,
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CP15_ISA_FEATURE_2,
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CP15_ISA_FEATURE_3,
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CP15_ISA_FEATURE_4,
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// c1 - Control registers
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CP15_CONTROL,
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CP15_AUXILIARY_CONTROL,
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CP15_COPROCESSOR_ACCESS_CONTROL,
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// c2 - Translation table registers
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CP15_TRANSLATION_BASE_TABLE_0,
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CP15_TRANSLATION_BASE_TABLE_1,
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CP15_TRANSLATION_BASE_CONTROL,
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CP15_DOMAIN_ACCESS_CONTROL,
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CP15_RESERVED,
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// c5 - Fault status registers
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CP15_FAULT_STATUS,
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CP15_INSTR_FAULT_STATUS,
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CP15_COMBINED_DATA_FSR = CP15_FAULT_STATUS,
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CP15_INST_FSR,
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// c6 - Fault Address registers
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CP15_FAULT_ADDRESS,
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CP15_COMBINED_DATA_FAR = CP15_FAULT_ADDRESS,
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CP15_WFAR,
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CP15_IFAR,
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// c7 - Cache operation registers
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CP15_WAIT_FOR_INTERRUPT,
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CP15_PHYS_ADDRESS,
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CP15_INVALIDATE_INSTR_CACHE,
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CP15_INVALIDATE_INSTR_CACHE_USING_MVA,
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CP15_INVALIDATE_INSTR_CACHE_USING_INDEX,
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CP15_FLUSH_PREFETCH_BUFFER,
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CP15_FLUSH_BRANCH_TARGET_CACHE,
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CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY,
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CP15_INVALIDATE_DATA_CACHE,
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CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA,
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CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX,
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CP15_INVALIDATE_DATA_AND_INSTR_CACHE,
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CP15_CLEAN_DATA_CACHE,
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CP15_CLEAN_DATA_CACHE_LINE_USING_MVA,
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CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX,
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CP15_DATA_SYNC_BARRIER,
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CP15_DATA_MEMORY_BARRIER,
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CP15_CLEAN_AND_INVALIDATE_DATA_CACHE,
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CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA,
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CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX,
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// c8 - TLB operations
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CP15_INVALIDATE_ITLB,
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CP15_INVALIDATE_ITLB_SINGLE_ENTRY,
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CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH,
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CP15_INVALIDATE_ITLB_ENTRY_ON_MVA,
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CP15_INVALIDATE_DTLB,
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CP15_INVALIDATE_DTLB_SINGLE_ENTRY,
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CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH,
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CP15_INVALIDATE_DTLB_ENTRY_ON_MVA,
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CP15_INVALIDATE_UTLB,
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CP15_INVALIDATE_UTLB_SINGLE_ENTRY,
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CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH,
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CP15_INVALIDATE_UTLB_ENTRY_ON_MVA,
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// c9 - Data cache lockdown register
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CP15_DATA_CACHE_LOCKDOWN,
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// c10 - TLB/Memory map registers
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CP15_TLB_LOCKDOWN,
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CP15_PRIMARY_REGION_REMAP,
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CP15_NORMAL_REGION_REMAP,
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// c13 - Thread related registers
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CP15_PID,
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CP15_CONTEXT_ID,
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CP15_THREAD_UPRW, // Thread ID register - User/Privileged Read/Write
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CP15_THREAD_URO, // Thread ID register - User Read Only (Privileged R/W)
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CP15_THREAD_PRW, // Thread ID register - Privileged R/W only.
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// c15 - Performance and TLB lockdown registers
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CP15_PERFORMANCE_MONITOR_CONTROL,
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CP15_CYCLE_COUNTER,
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CP15_COUNT_0,
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CP15_COUNT_1,
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CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY,
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CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY,
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CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS,
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CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS,
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CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE,
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CP15_TLB_DEBUG_CONTROL,
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// Skyeye defined
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CP15_TLB_FAULT_ADDR,
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CP15_TLB_FAULT_STATUS,
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// Not an actual register.
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// All registers should be defined above this.
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CP15_REGISTER_COUNT,
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};
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class DynarmicCP15 final : public Dynarmic::A32::Coprocessor {
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public:
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using CoprocReg = Dynarmic::A32::CoprocReg;
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explicit DynarmicCP15(u32* cp15) : CP15(cp15){};
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std::optional<Callback> CompileInternalOperation(bool two, unsigned opc1, CoprocReg CRd,
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CoprocReg CRn, CoprocReg CRm,
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unsigned opc2) override;
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CallbackOrAccessOneWord CompileSendOneWord(bool two, unsigned opc1, CoprocReg CRn,
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CoprocReg CRm, unsigned opc2) override;
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CallbackOrAccessTwoWords CompileSendTwoWords(bool two, unsigned opc, CoprocReg CRm) override;
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CallbackOrAccessOneWord CompileGetOneWord(bool two, unsigned opc1, CoprocReg CRn, CoprocReg CRm,
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unsigned opc2) override;
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CallbackOrAccessTwoWords CompileGetTwoWords(bool two, unsigned opc, CoprocReg CRm) override;
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std::optional<Callback> CompileLoadWords(bool two, bool long_transfer, CoprocReg CRd,
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std::optional<u8> option) override;
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std::optional<Callback> CompileStoreWords(bool two, bool long_transfer, CoprocReg CRd,
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std::optional<u8> option) override;
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private:
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u32* CP15{};
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};
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