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https://github.com/yuzu-emu/yuzu.git
synced 2024-08-23 14:00:44 +02:00
video_core: Allow copy elision to take place where applicable
Removes const from some variables that are returned from functions, as this allows the move assignment/constructors to execute for them.
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ad0b295125
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6adc824d9d
@ -1671,7 +1671,7 @@ std::string ARBDecompiler::HCastFloat(Operation operation) {
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}
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std::string ARBDecompiler::HUnpack(Operation operation) {
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const std::string operand = Visit(operation[0]);
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std::string operand = Visit(operation[0]);
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switch (std::get<Tegra::Shader::HalfType>(operation.GetMeta())) {
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case Tegra::Shader::HalfType::H0_H1:
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return operand;
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@ -2021,7 +2021,7 @@ std::string ARBDecompiler::InvocationId(Operation) {
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std::string ARBDecompiler::YNegate(Operation) {
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LOG_WARNING(Render_OpenGL, "(STUBBED)");
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const std::string temporary = AllocTemporary();
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std::string temporary = AllocTemporary();
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AddLine("MOV.F {}, 1;", temporary);
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return temporary;
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}
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@ -126,7 +126,7 @@ std::shared_ptr<Registry> MakeRegistry(const ShaderDiskCacheEntry& entry) {
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const VideoCore::GuestDriverProfile guest_profile{entry.texture_handler_size};
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const VideoCommon::Shader::SerializedRegistryInfo info{guest_profile, entry.bound_buffer,
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entry.graphics_info, entry.compute_info};
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const auto registry = std::make_shared<Registry>(entry.type, info);
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auto registry = std::make_shared<Registry>(entry.type, info);
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for (const auto& [address, value] : entry.keys) {
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const auto [buffer, offset] = address;
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registry->InsertKey(buffer, offset, value);
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@ -1912,7 +1912,7 @@ private:
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Expression Comparison(Operation operation) {
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static_assert(!unordered || type == Type::Float);
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const Expression expr = GenerateBinaryInfix(operation, op, Type::Bool, type, type);
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Expression expr = GenerateBinaryInfix(operation, op, Type::Bool, type, type);
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if constexpr (op.compare("!=") == 0 && type == Type::Float && !unordered) {
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// GLSL's operator!=(float, float) doesn't seem be ordered. This happens on both AMD's
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@ -98,12 +98,12 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) {
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op_b = GetOperandAbsNegInteger(op_b, false, instr.iadd3.neg_b, true);
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op_c = GetOperandAbsNegInteger(op_c, false, instr.iadd3.neg_c, true);
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const Node value = [&]() {
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const Node add_ab = Operation(OperationCode::IAdd, NO_PRECISE, op_a, op_b);
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const Node value = [&] {
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Node add_ab = Operation(OperationCode::IAdd, NO_PRECISE, op_a, op_b);
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if (opcode->get().GetId() != OpCode::Id::IADD3_R) {
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return Operation(OperationCode::IAdd, NO_PRECISE, add_ab, op_c);
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}
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const Node shifted = [&]() {
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const Node shifted = [&] {
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switch (instr.iadd3.mode) {
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case Tegra::Shader::IAdd3Mode::RightShift:
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// TODO(tech4me): According to
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@ -91,29 +91,28 @@ u32 ShaderIR::DecodeVideo(NodeBlock& bb, u32 pc) {
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return pc;
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}
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Node ShaderIR::GetVideoOperand(Node op, bool is_chunk, bool is_signed,
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Tegra::Shader::VideoType type, u64 byte_height) {
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Node ShaderIR::GetVideoOperand(Node op, bool is_chunk, bool is_signed, VideoType type,
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u64 byte_height) {
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if (!is_chunk) {
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return BitfieldExtract(op, static_cast<u32>(byte_height * 8), 8);
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}
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const Node zero = Immediate(0);
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switch (type) {
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case Tegra::Shader::VideoType::Size16_Low:
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case VideoType::Size16_Low:
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return BitfieldExtract(op, 0, 16);
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case Tegra::Shader::VideoType::Size16_High:
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case VideoType::Size16_High:
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return BitfieldExtract(op, 16, 16);
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case Tegra::Shader::VideoType::Size32:
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case VideoType::Size32:
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// TODO(Rodrigo): From my hardware tests it becomes a bit "mad" when this type is used
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// (1 * 1 + 0 == 0x5b800000). Until a better explanation is found: abort.
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UNIMPLEMENTED();
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return zero;
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case Tegra::Shader::VideoType::Invalid:
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return Immediate(0);
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case VideoType::Invalid:
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UNREACHABLE_MSG("Invalid instruction encoding");
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return zero;
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return Immediate(0);
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default:
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UNREACHABLE();
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return zero;
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return Immediate(0);
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}
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}
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@ -81,20 +81,21 @@ u32 ShaderIR::DecodeXmad(NodeBlock& bb, u32 pc) {
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SetTemporary(bb, 0, product);
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product = GetTemporary(0);
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const Node original_c = op_c;
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Node original_c = op_c;
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const Tegra::Shader::XmadMode set_mode = mode; // Workaround to clang compile error
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op_c = [&]() {
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op_c = [&] {
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switch (set_mode) {
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case Tegra::Shader::XmadMode::None:
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return original_c;
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case Tegra::Shader::XmadMode::CLo:
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return BitfieldExtract(original_c, 0, 16);
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return BitfieldExtract(std::move(original_c), 0, 16);
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case Tegra::Shader::XmadMode::CHi:
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return BitfieldExtract(original_c, 16, 16);
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return BitfieldExtract(std::move(original_c), 16, 16);
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case Tegra::Shader::XmadMode::CBcc: {
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const Node shifted_b = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed_b,
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original_b, Immediate(16));
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return SignedOperation(OperationCode::IAdd, is_signed_c, original_c, shifted_b);
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Node shifted_b = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed_b,
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original_b, Immediate(16));
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return SignedOperation(OperationCode::IAdd, is_signed_c, std::move(original_c),
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std::move(shifted_b));
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}
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case Tegra::Shader::XmadMode::CSfu: {
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const Node comp_a =
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@ -112,9 +112,9 @@ Node ShaderIR::GetOutputAttribute(Attribute::Index index, u64 element, Node buff
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}
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Node ShaderIR::GetInternalFlag(InternalFlag flag, bool negated) const {
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const Node node = MakeNode<InternalFlagNode>(flag);
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Node node = MakeNode<InternalFlagNode>(flag);
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if (negated) {
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return Operation(OperationCode::LogicalNegate, node);
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return Operation(OperationCode::LogicalNegate, std::move(node));
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}
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return node;
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}
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