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Merge pull request #388 from lioncash/sm
dyncom: Implement SMLAD/SMUAD/SMLSD/SMUSD
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commit
6ae381ac9e
@ -930,6 +930,8 @@ typedef struct _smlad_inst {
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unsigned int Rd;
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unsigned int Ra;
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unsigned int Rn;
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unsigned int op1;
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unsigned int op2;
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} smlad_inst;
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typedef struct _smla_inst {
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@ -2313,25 +2315,40 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(unsigned int inst, int index)
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlad)(unsigned int inst, int index){
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst));
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smlad_inst *inst_cream = (smlad_inst *)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlad)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst));
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smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->m = BIT(inst, 4);
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inst_cream->Rn = BITS(inst, 0, 3);
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inst_cream->Rm = BITS(inst, 8, 11);
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inst_cream->Rd = BITS(inst, 16, 19);
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inst_cream->Ra = BITS(inst, 12, 15);
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inst_cream->m = BIT(inst, 5);
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inst_cream->Rn = BITS(inst, 0, 3);
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inst_cream->Rm = BITS(inst, 8, 11);
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inst_cream->Rd = BITS(inst, 16, 19);
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inst_cream->Ra = BITS(inst, 12, 15);
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inst_cream->op1 = BITS(inst, 20, 22);
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inst_cream->op2 = BITS(inst, 5, 7);
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if (CHECK_RM )
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inst_base->load_r15 = 1;
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smuad)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(smlad)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(smlad)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlsd)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(smlad)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst));
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@ -2355,12 +2372,10 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index)
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLALXY"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLALD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLAW"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlsd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLSD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smlsld)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMLSLD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMMLA"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smmls)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMMLS"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smmul)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMMUL"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smuad)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMUAD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(smul)(unsigned int inst, int index)
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{
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arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smul_inst));
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@ -2423,7 +2438,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index)
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inst_base->load_r15 = 1;
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SMUSD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SRS"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index)
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{
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@ -5382,44 +5396,59 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SMLAD_INST:
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SMLSD_INST:
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SMUAD_INST:
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SMUSD_INST:
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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smlad_inst *inst_cream = (smlad_inst *)inst_base->component;
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long long int rm = cpu->Reg[inst_cream->Rm];
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long long int rn = cpu->Reg[inst_cream->Rn];
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long long int ra = cpu->Reg[inst_cream->Ra];
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
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const u8 op2 = inst_cream->op2;
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// See SMUAD
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if(inst_cream->Ra == 15)
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CITRA_IGNORE_EXIT(-1);
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int operand2 = (inst_cream->m)? ROTATE_RIGHT_32(rm, 16):rm;
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int half_rn, half_operand2;
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u32 rm_val = cpu->Reg[inst_cream->Rm];
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const u32 rn_val = cpu->Reg[inst_cream->Rn];
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half_rn = rn & 0xFFFF;
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half_rn = (half_rn & 0x8000)? (0xFFFF0000|half_rn) : half_rn;
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if (inst_cream->m)
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rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16));
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half_operand2 = operand2 & 0xFFFF;
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half_operand2 = (half_operand2 & 0x8000)? (0xFFFF0000|half_operand2) : half_operand2;
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const s16 rm_lo = (rm_val & 0xFFFF);
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const s16 rm_hi = ((rm_val >> 16) & 0xFFFF);
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const s16 rn_lo = (rn_val & 0xFFFF);
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const s16 rn_hi = ((rn_val >> 16) & 0xFFFF);
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long long int product1 = half_rn * half_operand2;
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const u32 product1 = (rn_lo * rm_lo);
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const u32 product2 = (rn_hi * rm_hi);
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half_rn = (rn & 0xFFFF0000) >> 16;
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half_rn = (half_rn & 0x8000)? (0xFFFF0000|half_rn) : half_rn;
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// SMUAD and SMLAD
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if (BIT(op2, 1) == 0) {
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RD = (product1 + product2);
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half_operand2 = (operand2 & 0xFFFF0000) >> 16;
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half_operand2 = (half_operand2 & 0x8000)? (0xFFFF0000|half_operand2) : half_operand2;
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if (inst_cream->Ra != 15) {
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RD += cpu->Reg[inst_cream->Ra];
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long long int product2 = half_rn * half_operand2;
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if (ARMul_AddOverflowQ(product1 + product2, cpu->Reg[inst_cream->Ra]))
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cpu->Cpsr |= (1 << 27);
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}
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long long int signed_ra = (ra & 0x80000000)? (0xFFFFFFFF00000000LL) | ra : ra;
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long long int result = product1 + product2 + signed_ra;
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cpu->Reg[inst_cream->Rd] = result & 0xFFFFFFFF;
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if (ARMul_AddOverflowQ(product1, product2))
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cpu->Cpsr |= (1 << 27);
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}
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// SMUSD and SMLSD
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else {
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RD = (product1 - product2);
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// TODO: FIXME should check Signed overflow
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if (inst_cream->Ra != 15) {
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RD += cpu->Reg[inst_cream->Ra];
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if (ARMul_AddOverflowQ(product1 - product2, cpu->Reg[inst_cream->Ra]))
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cpu->Cpsr |= (1 << 27);
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}
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}
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(umlal_inst));
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INC_PC(sizeof(smlad_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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@ -5452,15 +5481,15 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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SMLALXY_INST:
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SMLALD_INST:
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SMLAW_INST:
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SMLSD_INST:
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SMLSLD_INST:
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SMMLA_INST:
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SMMLS_INST:
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SMMUL_INST:
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SMUAD_INST:
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SMUL_INST:
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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@ -5528,8 +5557,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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GOTO_NEXT_INST;
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}
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SMUSD_INST:
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SRS_INST:
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SSAT_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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@ -6470,17 +6470,23 @@ L_stm_s_takeabort:
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if (BITS(12, 15) != 15) {
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state->Reg[rd_idx] += state->Reg[ra_idx];
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ARMul_AddOverflowQ(state, product1 + product2, state->Reg[ra_idx]);
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if (ARMul_AddOverflowQ(product1 + product2, state->Reg[ra_idx]))
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SETQ;
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}
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ARMul_AddOverflowQ(state, product1, product2);
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if (ARMul_AddOverflowQ(product1, product2))
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SETQ;
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}
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// SMUSD and SMLSD
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else {
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state->Reg[rd_idx] = product1 - product2;
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if (BITS(12, 15) != 15)
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if (BITS(12, 15) != 15) {
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state->Reg[rd_idx] += state->Reg[ra_idx];
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if (ARMul_AddOverflowQ(product1 - product2, state->Reg[ra_idx]))
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SETQ;
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}
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}
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return 1;
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@ -453,12 +453,14 @@ ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
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ASSIGNV (AddOverflow (a, b, result));
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}
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/* Assigns the Q flag if the given result is considered an overflow from the addition of a and b */
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void ARMul_AddOverflowQ(ARMul_State* state, ARMword a, ARMword b)
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// Returns true if the Q flag should be set as a result of overflow.
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bool ARMul_AddOverflowQ(ARMword a, ARMword b)
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{
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u32 result = a + b;
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if (((result ^ a) & (u32)0x80000000) && ((a ^ b) & (u32)0x80000000) == 0)
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SETQ;
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return true;
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return false;
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}
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/* Assigns the C flag after an subtraction of a and b to give result. */
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@ -790,6 +790,8 @@ extern void ARMul_FixSPSR(ARMul_State*, ARMword, ARMword);
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extern void ARMul_ConsolePrint(ARMul_State*, const char*, ...);
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extern void ARMul_SelectProcessor(ARMul_State*, unsigned);
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extern bool ARMul_AddOverflowQ(ARMword, ARMword);
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extern u8 ARMul_SignedSaturatedAdd8(u8, u8);
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extern u8 ARMul_SignedSaturatedSub8(u8, u8);
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extern u16 ARMul_SignedSaturatedAdd16(u16, u16);
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@ -602,7 +602,6 @@ extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
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extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword);
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extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword);
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extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword);
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extern void ARMul_AddOverflowQ(ARMul_State*, ARMword, ARMword);
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extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword);
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extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword);
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extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *);
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