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shader/half_set_predicate: Implement missing HSETP2 variants
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@ -931,8 +931,6 @@ union Instruction {
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} csetp;
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} csetp;
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union {
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union {
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BitField<35, 4, PredCondition> cond;
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BitField<49, 1, u64> h_and;
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BitField<6, 1, u64> ftz;
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BitField<6, 1, u64> ftz;
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BitField<45, 2, PredOperation> op;
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BitField<45, 2, PredOperation> op;
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BitField<3, 3, u64> pred3;
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BitField<3, 3, u64> pred3;
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@ -940,9 +938,21 @@ union Instruction {
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BitField<43, 1, u64> negate_a;
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BitField<43, 1, u64> negate_a;
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BitField<44, 1, u64> abs_a;
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BitField<44, 1, u64> abs_a;
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BitField<47, 2, HalfType> type_a;
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BitField<47, 2, HalfType> type_a;
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BitField<31, 1, u64> negate_b;
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union {
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BitField<30, 1, u64> abs_b;
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BitField<35, 4, PredCondition> cond;
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BitField<28, 2, HalfType> type_b;
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BitField<49, 1, u64> h_and;
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BitField<31, 1, u64> negate_b;
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BitField<30, 1, u64> abs_b;
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BitField<28, 2, HalfType> type_b;
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} reg;
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union {
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BitField<56, 1, u64> negate_b;
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BitField<54, 1, u64> abs_b;
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} cbuf;
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union {
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BitField<49, 4, PredCondition> cond;
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BitField<53, 1, u64> h_and;
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} cbuf_and_imm;
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BitField<42, 1, u64> neg_pred;
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BitField<42, 1, u64> neg_pred;
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BitField<39, 3, u64> pred39;
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BitField<39, 3, u64> pred39;
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} hsetp2;
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} hsetp2;
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@ -1548,7 +1558,9 @@ public:
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HFMA2_RC,
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HFMA2_RC,
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HFMA2_RR,
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HFMA2_RR,
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HFMA2_IMM_R,
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HFMA2_IMM_R,
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HSETP2_C,
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HSETP2_R,
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HSETP2_R,
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HSETP2_IMM,
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HSET2_R,
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HSET2_R,
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POPC_C,
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POPC_C,
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POPC_R,
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POPC_R,
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@ -1831,7 +1843,9 @@ private:
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INST("01100---1-------", Id::HFMA2_RC, Type::Hfma2, "HFMA2_RC"),
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INST("01100---1-------", Id::HFMA2_RC, Type::Hfma2, "HFMA2_RC"),
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INST("0101110100000---", Id::HFMA2_RR, Type::Hfma2, "HFMA2_RR"),
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INST("0101110100000---", Id::HFMA2_RR, Type::Hfma2, "HFMA2_RR"),
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INST("01110---0-------", Id::HFMA2_IMM_R, Type::Hfma2, "HFMA2_R_IMM"),
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INST("01110---0-------", Id::HFMA2_IMM_R, Type::Hfma2, "HFMA2_R_IMM"),
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INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP_R"),
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INST("0111111-1-------", Id::HSETP2_C, Type::HalfSetPredicate, "HSETP2_C"),
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INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP2_R"),
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INST("0111111-0-------", Id::HSETP2_IMM, Type::HalfSetPredicate, "HSETP2_IMM"),
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INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"),
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INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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@ -23,17 +23,33 @@ u32 ShaderIR::DecodeHalfSetPredicate(NodeBlock& bb, u32 pc) {
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Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hsetp2.type_a);
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Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hsetp2.type_a);
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op_a = GetOperandAbsNegHalf(op_a, instr.hsetp2.abs_a, instr.hsetp2.negate_a);
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op_a = GetOperandAbsNegHalf(op_a, instr.hsetp2.abs_a, instr.hsetp2.negate_a);
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Node op_b = [&]() {
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Tegra::Shader::PredCondition cond{};
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switch (opcode->get().GetId()) {
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bool h_and{};
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case OpCode::Id::HSETP2_R:
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Node op_b{};
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return GetOperandAbsNegHalf(GetRegister(instr.gpr20), instr.hsetp2.abs_a,
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switch (opcode->get().GetId()) {
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instr.hsetp2.negate_b);
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case OpCode::Id::HSETP2_C:
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default:
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cond = instr.hsetp2.cbuf_and_imm.cond;
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UNREACHABLE();
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h_and = instr.hsetp2.cbuf_and_imm.h_and;
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return Immediate(0);
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op_b = GetOperandAbsNegHalf(GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset),
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}
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instr.hsetp2.cbuf.abs_b, instr.hsetp2.cbuf.negate_b);
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}();
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break;
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op_b = UnpackHalfFloat(op_b, instr.hsetp2.type_b);
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case OpCode::Id::HSETP2_IMM:
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cond = instr.hsetp2.cbuf_and_imm.cond;
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h_and = instr.hsetp2.cbuf_and_imm.h_and;
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op_b = UnpackHalfImmediate(instr, true);
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break;
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case OpCode::Id::HSETP2_R:
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cond = instr.hsetp2.reg.cond;
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h_and = instr.hsetp2.reg.h_and;
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op_b =
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UnpackHalfFloat(GetOperandAbsNegHalf(GetRegister(instr.gpr20), instr.hsetp2.reg.abs_b,
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instr.hsetp2.reg.negate_b),
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instr.hsetp2.reg.type_b);
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break;
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default:
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UNREACHABLE();
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op_b = Immediate(0);
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}
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// We can't use the constant predicate as destination.
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// We can't use the constant predicate as destination.
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ASSERT(instr.hsetp2.pred3 != static_cast<u64>(Pred::UnusedIndex));
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ASSERT(instr.hsetp2.pred3 != static_cast<u64>(Pred::UnusedIndex));
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@ -42,9 +58,9 @@ u32 ShaderIR::DecodeHalfSetPredicate(NodeBlock& bb, u32 pc) {
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const OperationCode combiner = GetPredicateCombiner(instr.hsetp2.op);
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const OperationCode combiner = GetPredicateCombiner(instr.hsetp2.op);
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const OperationCode pair_combiner =
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const OperationCode pair_combiner =
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instr.hsetp2.h_and ? OperationCode::LogicalAll2 : OperationCode::LogicalAny2;
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h_and ? OperationCode::LogicalAll2 : OperationCode::LogicalAny2;
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const Node comparison = GetPredicateComparisonHalf(instr.hsetp2.cond, op_a, op_b);
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const Node comparison = GetPredicateComparisonHalf(cond, op_a, op_b);
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const Node first_pred = Operation(pair_combiner, comparison);
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const Node first_pred = Operation(pair_combiner, comparison);
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// Set the primary predicate to the result of Predicate OP SecondPredicate
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// Set the primary predicate to the result of Predicate OP SecondPredicate
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