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vfp: Implement VMOVBRRSS
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6ce4b7b666
@ -141,7 +141,7 @@ unsigned VFPMRRC(ARMul_State* state, unsigned type, u32 instr, u32* value1, u32*
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{
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if (CoProc == 10 && (OPC_1 & 0xD) == 1)
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{
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VFP_DEBUG_UNIMPLEMENTED(VMOVBRRSS);
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VMOVBRRSS(state, BIT(20), Rt, Rt2, BIT(5)<<4|CRm, value1, value2);
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return ARMul_DONE;
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}
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@ -175,7 +175,7 @@ unsigned VFPMCRR(ARMul_State* state, unsigned type, u32 instr, u32 value1, u32 v
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{
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if (CoProc == 10 && (OPC_1 & 0xD) == 1)
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{
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VFP_DEBUG_UNIMPLEMENTED(VMOVBRRSS);
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VMOVBRRSS(state, BIT(20), Rt, Rt2, BIT(5)<<4|CRm, &value1, &value2);
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return ARMul_DONE;
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}
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@ -504,6 +504,22 @@ void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword
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state->ExtReg[n*2] = *value1;
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}
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}
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void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
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{
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DBG("VMOV(BRRSS) :\n");
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if (to_arm)
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{
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DBG("\tr[%d-%d] <= s[%d-%d]=[%x-%x]\n", t2, t, n+1, n, state->ExtReg[n+1], state->ExtReg[n]);
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*value1 = state->ExtReg[n+0];
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*value2 = state->ExtReg[n+1];
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}
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else
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{
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DBG("\ts[%d-%d] <= r[%d-%d]=[%x-%x]\n", n+1, n, t2, t, *value2, *value1);
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state->ExtReg[n+0] = *value1;
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state->ExtReg[n+1] = *value2;
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}
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}
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/* ----------- MCR ------------ */
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void VMSR(ARMul_State* state, ARMword reg, ARMword Rt)
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@ -97,6 +97,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
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void VMRS(ARMul_State * state, ARMword reg, ARMword Rt, ARMword *value);
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void VMOVBRS(ARMul_State * state, ARMword to_arm, ARMword t, ARMword n, ARMword *value);
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void VMOVBRRD(ARMul_State * state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword *value1, ARMword *value2);
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void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
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void VMOVI(ARMul_State * state, ARMword single, ARMword d, ARMword imm);
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void VMOVR(ARMul_State * state, ARMword single, ARMword d, ARMword imm);
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/* MCR */
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@ -2702,7 +2702,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrss)(unsigned int inst, int index)
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inst_cream->t = BITS(inst, 12, 15);
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inst_cream->t2 = BITS(inst, 16, 19);
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inst_cream->m = BITS(inst, 0, 3)<<1|BIT(inst, 5);
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return inst_base;
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}
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#endif
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@ -2711,10 +2711,11 @@ VMOVBRRSS_INST:
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{
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if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
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CHECK_VFP_ENABLED;
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vmovbrrss_inst *inst_cream = (vmovbrrss_inst *)inst_base->component;
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VFP_DEBUG_UNIMPLEMENTED(VMOVBRRSS);
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vmovbrrss_inst* const inst_cream = (vmovbrrss_inst*)inst_base->component;
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VMOVBRRSS(cpu, inst_cream->to_arm, inst_cream->t, inst_cream->t2, inst_cream->m,
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&cpu->Reg[inst_cream->t], &cpu->Reg[inst_cream->t2]);
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(vmovbrrss_inst));
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@ -2729,15 +2730,29 @@ DYNCOM_FILL_ACTION(vmovbrrss),
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int DYNCOM_TAG(vmovbrrss)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
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{
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int instr_size = INSTR_SIZE;
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DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
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arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
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arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
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if (instr >> 28 != 0xE)
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*tag |= TAG_CONDITIONAL;
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return instr_size;
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}
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#endif
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#ifdef VFP_DYNCOM_TRANS
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int DYNCOM_TRANS(vmovbrrss)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
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DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
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arch_arm_undef(cpu, bb, instr);
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int DYNCOM_TRANS(vmovbrrss)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc)
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{
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int to_arm = BIT(20) == 1;
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int t = BITS(12, 15);
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int t2 = BITS(16, 19);
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int n = BIT(5)<<4 | BITS(0, 3);
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if (to_arm) {
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LET(t, IBITCAST32(FR32(n + 0)));
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LET(t2, IBITCAST32(FR32(n + 1)));
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}
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else {
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LETFPS(n + 0, FPBITCAST32(R(t)));
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LETFPS(n + 1, FPBITCAST32(R(t2)));
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}
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return No_exp;
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}
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#endif
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