mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-08-21 22:33:22 +02:00
spirv: Add lower fp16 to fp32 pass
This commit is contained in:
parent
85cce78583
commit
6db69990da
@ -7,6 +7,7 @@ add_library(shader_recompiler STATIC
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backend/spirv/emit_spirv_composite.cpp
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backend/spirv/emit_spirv_context_get_set.cpp
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backend/spirv/emit_spirv_control_flow.cpp
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backend/spirv/emit_spirv_convert.cpp
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backend/spirv/emit_spirv_floating_point.cpp
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backend/spirv/emit_spirv_integer.cpp
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backend/spirv/emit_spirv_logical.cpp
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@ -82,6 +83,7 @@ add_library(shader_recompiler STATIC
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ir_opt/dead_code_elimination_pass.cpp
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ir_opt/global_memory_to_storage_buffer_pass.cpp
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ir_opt/identity_removal_pass.cpp
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ir_opt/lower_fp16_to_fp32.cpp
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ir_opt/passes.h
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ir_opt/ssa_rewrite_pass.cpp
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ir_opt/verification_pass.cpp
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@ -30,8 +30,11 @@ EmitContext::EmitContext(IR::Program& program) : Sirit::Module(0x00010000) {
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DefineCommonTypes(program.info);
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DefineCommonConstants();
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DefineSpecialVariables(program.info);
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DefineConstantBuffers(program.info);
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DefineStorageBuffers(program.info);
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u32 binding{};
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DefineConstantBuffers(program.info, binding);
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DefineStorageBuffers(program.info, binding);
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DefineLabels(program);
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}
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@ -58,6 +61,12 @@ void EmitContext::DefineCommonTypes(const Info& info) {
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U1 = Name(TypeBool(), "u1");
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// TODO: Conditionally define these
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AddCapability(spv::Capability::Int16);
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AddCapability(spv::Capability::Int64);
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U16 = Name(TypeInt(16, false), "u16");
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U64 = Name(TypeInt(64, false), "u64");
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F32.Define(*this, TypeFloat(32), "f32");
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U32.Define(*this, TypeInt(32, false), "u32");
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@ -95,12 +104,12 @@ void EmitContext::DefineSpecialVariables(const Info& info) {
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}
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}
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void EmitContext::DefineConstantBuffers(const Info& info) {
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void EmitContext::DefineConstantBuffers(const Info& info, u32& binding) {
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if (info.constant_buffer_descriptors.empty()) {
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return;
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}
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const Id array_type{TypeArray(U32[1], Constant(U32[1], 4096))};
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Decorate(array_type, spv::Decoration::ArrayStride, 16U);
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Decorate(array_type, spv::Decoration::ArrayStride, 4U);
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const Id struct_type{TypeStruct(array_type)};
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Name(struct_type, "cbuf_block");
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@ -111,18 +120,19 @@ void EmitContext::DefineConstantBuffers(const Info& info) {
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const Id uniform_type{TypePointer(spv::StorageClass::Uniform, struct_type)};
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uniform_u32 = TypePointer(spv::StorageClass::Uniform, U32[1]);
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u32 binding{};
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u32 index{};
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for (const Info::ConstantBufferDescriptor& desc : info.constant_buffer_descriptors) {
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const Id id{AddGlobalVariable(uniform_type, spv::StorageClass::Uniform)};
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Decorate(id, spv::Decoration::Binding, binding);
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Decorate(id, spv::Decoration::DescriptorSet, 0U);
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Name(id, fmt::format("c{}", desc.index));
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std::fill_n(cbufs.data() + desc.index, desc.count, id);
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index += desc.count;
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binding += desc.count;
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}
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}
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void EmitContext::DefineStorageBuffers(const Info& info) {
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void EmitContext::DefineStorageBuffers(const Info& info, u32& binding) {
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if (info.storage_buffers_descriptors.empty()) {
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return;
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}
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@ -140,13 +150,14 @@ void EmitContext::DefineStorageBuffers(const Info& info) {
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const Id storage_type{TypePointer(spv::StorageClass::StorageBuffer, struct_type)};
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storage_u32 = TypePointer(spv::StorageClass::StorageBuffer, U32[1]);
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u32 binding{};
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u32 index{};
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for (const Info::StorageBufferDescriptor& desc : info.storage_buffers_descriptors) {
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const Id id{AddGlobalVariable(storage_type, spv::StorageClass::StorageBuffer)};
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Decorate(id, spv::Decoration::Binding, binding);
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Decorate(id, spv::Decoration::DescriptorSet, 0U);
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Name(id, fmt::format("ssbo{}", binding));
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std::fill_n(ssbos.data() + binding, desc.count, id);
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Name(id, fmt::format("ssbo{}", index));
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std::fill_n(ssbos.data() + index, desc.count, id);
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index += desc.count;
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binding += desc.count;
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}
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}
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@ -37,6 +37,8 @@ public:
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Id void_id{};
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Id U1{};
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Id U16{};
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Id U64{};
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VectorTypes F32;
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VectorTypes U32;
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VectorTypes F16;
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@ -59,8 +61,8 @@ private:
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void DefineCommonTypes(const Info& info);
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void DefineCommonConstants();
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void DefineSpecialVariables(const Info& info);
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void DefineConstantBuffers(const Info& info);
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void DefineStorageBuffers(const Info& info);
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void DefineConstantBuffers(const Info& info, u32& binding);
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void DefineStorageBuffers(const Info& info, u32& binding);
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void DefineLabels(IR::Program& program);
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};
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@ -14,6 +14,8 @@
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#include "shader_recompiler/frontend/ir/microinstruction.h"
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#include "shader_recompiler/frontend/ir/program.h"
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#pragma optimize("", off)
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namespace Shader::Backend::SPIRV {
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namespace {
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template <class Func>
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@ -79,26 +79,27 @@ void EmitWriteStorageU16(EmitContext& ctx);
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void EmitWriteStorageS16(EmitContext& ctx);
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void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value);
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void EmitWriteStorage64(EmitContext& ctx);
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void EmitWriteStorage64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value);
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void EmitWriteStorage128(EmitContext& ctx);
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void EmitCompositeConstructU32x2(EmitContext& ctx);
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void EmitCompositeConstructU32x3(EmitContext& ctx);
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void EmitCompositeConstructU32x4(EmitContext& ctx);
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void EmitCompositeExtractU32x2(EmitContext& ctx);
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Id EmitCompositeExtractU32x3(EmitContext& ctx, Id vector, u32 index);
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void EmitCompositeExtractU32x4(EmitContext& ctx);
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Id EmitCompositeConstructU32x2(EmitContext& ctx, Id e1, Id e2);
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Id EmitCompositeConstructU32x3(EmitContext& ctx, Id e1, Id e2, Id e3);
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Id EmitCompositeConstructU32x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4);
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Id EmitCompositeExtractU32x2(EmitContext& ctx, Id composite, u32 index);
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Id EmitCompositeExtractU32x3(EmitContext& ctx, Id composite, u32 index);
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Id EmitCompositeExtractU32x4(EmitContext& ctx, Id composite, u32 index);
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void EmitCompositeConstructF16x2(EmitContext& ctx);
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void EmitCompositeConstructF16x3(EmitContext& ctx);
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void EmitCompositeConstructF16x4(EmitContext& ctx);
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void EmitCompositeExtractF16x2(EmitContext& ctx);
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void EmitCompositeExtractF16x3(EmitContext& ctx);
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void EmitCompositeExtractF16x4(EmitContext& ctx);
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Id EmitCompositeExtractF16x2(EmitContext& ctx, Id composite, u32 index);
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Id EmitCompositeExtractF16x3(EmitContext& ctx, Id composite, u32 index);
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Id EmitCompositeExtractF16x4(EmitContext& ctx, Id composite, u32 index);
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void EmitCompositeConstructF32x2(EmitContext& ctx);
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void EmitCompositeConstructF32x3(EmitContext& ctx);
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void EmitCompositeConstructF32x4(EmitContext& ctx);
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void EmitCompositeExtractF32x2(EmitContext& ctx);
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void EmitCompositeExtractF32x3(EmitContext& ctx);
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void EmitCompositeExtractF32x4(EmitContext& ctx);
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Id EmitCompositeExtractF32x2(EmitContext& ctx, Id composite, u32 index);
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Id EmitCompositeExtractF32x3(EmitContext& ctx, Id composite, u32 index);
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Id EmitCompositeExtractF32x4(EmitContext& ctx, Id composite, u32 index);
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void EmitCompositeConstructF64x2(EmitContext& ctx);
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void EmitCompositeConstructF64x3(EmitContext& ctx);
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void EmitCompositeConstructF64x4(EmitContext& ctx);
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@ -116,11 +117,13 @@ void EmitBitCastF16U16(EmitContext& ctx);
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Id EmitBitCastF32U32(EmitContext& ctx, Id value);
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void EmitBitCastF64U64(EmitContext& ctx);
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void EmitPackUint2x32(EmitContext& ctx);
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void EmitUnpackUint2x32(EmitContext& ctx);
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void EmitPackFloat2x16(EmitContext& ctx);
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void EmitUnpackFloat2x16(EmitContext& ctx);
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void EmitPackDouble2x32(EmitContext& ctx);
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void EmitUnpackDouble2x32(EmitContext& ctx);
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Id EmitUnpackUint2x32(EmitContext& ctx, Id value);
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Id EmitPackFloat2x16(EmitContext& ctx, Id value);
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Id EmitUnpackFloat2x16(EmitContext& ctx, Id value);
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Id EmitPackHalf2x16(EmitContext& ctx, Id value);
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Id EmitUnpackHalf2x16(EmitContext& ctx, Id value);
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Id EmitPackDouble2x32(EmitContext& ctx, Id value);
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Id EmitUnpackDouble2x32(EmitContext& ctx, Id value);
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void EmitGetZeroFromOp(EmitContext& ctx);
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void EmitGetSignFromOp(EmitContext& ctx);
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void EmitGetCarryFromOp(EmitContext& ctx);
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@ -159,18 +162,18 @@ void EmitFPLog2(EmitContext& ctx);
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void EmitFPSaturate16(EmitContext& ctx);
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void EmitFPSaturate32(EmitContext& ctx);
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void EmitFPSaturate64(EmitContext& ctx);
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void EmitFPRoundEven16(EmitContext& ctx);
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void EmitFPRoundEven32(EmitContext& ctx);
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void EmitFPRoundEven64(EmitContext& ctx);
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void EmitFPFloor16(EmitContext& ctx);
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void EmitFPFloor32(EmitContext& ctx);
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void EmitFPFloor64(EmitContext& ctx);
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void EmitFPCeil16(EmitContext& ctx);
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void EmitFPCeil32(EmitContext& ctx);
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void EmitFPCeil64(EmitContext& ctx);
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void EmitFPTrunc16(EmitContext& ctx);
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void EmitFPTrunc32(EmitContext& ctx);
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void EmitFPTrunc64(EmitContext& ctx);
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Id EmitFPRoundEven16(EmitContext& ctx, Id value);
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Id EmitFPRoundEven32(EmitContext& ctx, Id value);
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Id EmitFPRoundEven64(EmitContext& ctx, Id value);
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Id EmitFPFloor16(EmitContext& ctx, Id value);
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Id EmitFPFloor32(EmitContext& ctx, Id value);
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Id EmitFPFloor64(EmitContext& ctx, Id value);
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Id EmitFPCeil16(EmitContext& ctx, Id value);
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Id EmitFPCeil32(EmitContext& ctx, Id value);
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Id EmitFPCeil64(EmitContext& ctx, Id value);
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Id EmitFPTrunc16(EmitContext& ctx, Id value);
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Id EmitFPTrunc32(EmitContext& ctx, Id value);
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Id EmitFPTrunc64(EmitContext& ctx, Id value);
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Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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void EmitIAdd64(EmitContext& ctx);
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Id EmitISub32(EmitContext& ctx, Id a, Id b);
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@ -201,25 +204,25 @@ void EmitLogicalOr(EmitContext& ctx);
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void EmitLogicalAnd(EmitContext& ctx);
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void EmitLogicalXor(EmitContext& ctx);
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void EmitLogicalNot(EmitContext& ctx);
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void EmitConvertS16F16(EmitContext& ctx);
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void EmitConvertS16F32(EmitContext& ctx);
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void EmitConvertS16F64(EmitContext& ctx);
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void EmitConvertS32F16(EmitContext& ctx);
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void EmitConvertS32F32(EmitContext& ctx);
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void EmitConvertS32F64(EmitContext& ctx);
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void EmitConvertS64F16(EmitContext& ctx);
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void EmitConvertS64F32(EmitContext& ctx);
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void EmitConvertS64F64(EmitContext& ctx);
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void EmitConvertU16F16(EmitContext& ctx);
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void EmitConvertU16F32(EmitContext& ctx);
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void EmitConvertU16F64(EmitContext& ctx);
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void EmitConvertU32F16(EmitContext& ctx);
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void EmitConvertU32F32(EmitContext& ctx);
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void EmitConvertU32F64(EmitContext& ctx);
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void EmitConvertU64F16(EmitContext& ctx);
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void EmitConvertU64F32(EmitContext& ctx);
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void EmitConvertU64F64(EmitContext& ctx);
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void EmitConvertU64U32(EmitContext& ctx);
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void EmitConvertU32U64(EmitContext& ctx);
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Id EmitConvertS16F16(EmitContext& ctx, Id value);
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Id EmitConvertS16F32(EmitContext& ctx, Id value);
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Id EmitConvertS16F64(EmitContext& ctx, Id value);
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Id EmitConvertS32F16(EmitContext& ctx, Id value);
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Id EmitConvertS32F32(EmitContext& ctx, Id value);
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Id EmitConvertS32F64(EmitContext& ctx, Id value);
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Id EmitConvertS64F16(EmitContext& ctx, Id value);
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Id EmitConvertS64F32(EmitContext& ctx, Id value);
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Id EmitConvertS64F64(EmitContext& ctx, Id value);
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Id EmitConvertU16F16(EmitContext& ctx, Id value);
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Id EmitConvertU16F32(EmitContext& ctx, Id value);
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Id EmitConvertU16F64(EmitContext& ctx, Id value);
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Id EmitConvertU32F16(EmitContext& ctx, Id value);
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Id EmitConvertU32F32(EmitContext& ctx, Id value);
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Id EmitConvertU32F64(EmitContext& ctx, Id value);
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Id EmitConvertU64F16(EmitContext& ctx, Id value);
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Id EmitConvertU64F32(EmitContext& ctx, Id value);
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Id EmitConvertU64F64(EmitContext& ctx, Id value);
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Id EmitConvertU64U32(EmitContext& ctx, Id value);
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Id EmitConvertU32U64(EmitContext& ctx, Id value);
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} // namespace Shader::Backend::SPIRV
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@ -34,24 +34,32 @@ void EmitPackUint2x32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitUnpackUint2x32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitUnpackUint2x32(EmitContext& ctx, Id value) {
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return ctx.OpBitcast(ctx.U32[2], value);
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}
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void EmitPackFloat2x16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitPackFloat2x16(EmitContext& ctx, Id value) {
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return ctx.OpBitcast(ctx.U32[1], value);
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}
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void EmitUnpackFloat2x16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitUnpackFloat2x16(EmitContext& ctx, Id value) {
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return ctx.OpBitcast(ctx.F16[2], value);
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}
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void EmitPackDouble2x32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitPackHalf2x16(EmitContext& ctx, Id value) {
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return ctx.OpPackHalf2x16(ctx.U32[1], value);
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}
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void EmitUnpackDouble2x32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitUnpackHalf2x16(EmitContext& ctx, Id value) {
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return ctx.OpUnpackHalf2x16(ctx.F32[2], value);
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}
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Id EmitPackDouble2x32(EmitContext& ctx, Id value) {
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return ctx.OpBitcast(ctx.F64[1], value);
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}
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Id EmitUnpackDouble2x32(EmitContext& ctx, Id value) {
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return ctx.OpBitcast(ctx.U32[2], value);
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}
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} // namespace Shader::Backend::SPIRV
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@ -6,28 +6,28 @@
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namespace Shader::Backend::SPIRV {
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void EmitCompositeConstructU32x2(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitCompositeConstructU32x2(EmitContext& ctx, Id e1, Id e2) {
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return ctx.OpCompositeConstruct(ctx.U32[2], e1, e2);
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}
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void EmitCompositeConstructU32x3(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitCompositeConstructU32x3(EmitContext& ctx, Id e1, Id e2, Id e3) {
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return ctx.OpCompositeConstruct(ctx.U32[3], e1, e2, e3);
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}
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void EmitCompositeConstructU32x4(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitCompositeConstructU32x4(EmitContext& ctx, Id e1, Id e2, Id e3, Id e4) {
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return ctx.OpCompositeConstruct(ctx.U32[4], e1, e2, e3, e4);
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}
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void EmitCompositeExtractU32x2(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitCompositeExtractU32x2(EmitContext& ctx, Id composite, u32 index) {
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return ctx.OpCompositeExtract(ctx.U32[1], composite, index);
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}
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Id EmitCompositeExtractU32x3(EmitContext& ctx, Id vector, u32 index) {
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return ctx.OpCompositeExtract(ctx.U32[1], vector, index);
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Id EmitCompositeExtractU32x3(EmitContext& ctx, Id composite, u32 index) {
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return ctx.OpCompositeExtract(ctx.U32[1], composite, index);
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}
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void EmitCompositeExtractU32x4(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitCompositeExtractU32x4(EmitContext& ctx, Id composite, u32 index) {
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return ctx.OpCompositeExtract(ctx.U32[1], composite, index);
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}
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void EmitCompositeConstructF16x2(EmitContext&) {
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@ -42,16 +42,16 @@ void EmitCompositeConstructF16x4(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitCompositeExtractF16x2(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitCompositeExtractF16x2(EmitContext& ctx, Id composite, u32 index) {
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return ctx.OpCompositeExtract(ctx.F16[1], composite, index);
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}
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void EmitCompositeExtractF16x3(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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Id EmitCompositeExtractF16x3(EmitContext& ctx, Id composite, u32 index) {
|
||||
return ctx.OpCompositeExtract(ctx.F16[1], composite, index);
|
||||
}
|
||||
|
||||
void EmitCompositeExtractF16x4(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitCompositeExtractF16x4(EmitContext& ctx, Id composite, u32 index) {
|
||||
return ctx.OpCompositeExtract(ctx.F16[1], composite, index);
|
||||
}
|
||||
|
||||
void EmitCompositeConstructF32x2(EmitContext&) {
|
||||
@ -66,16 +66,16 @@ void EmitCompositeConstructF32x4(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitCompositeExtractF32x2(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitCompositeExtractF32x2(EmitContext& ctx, Id composite, u32 index) {
|
||||
return ctx.OpCompositeExtract(ctx.F32[1], composite, index);
|
||||
}
|
||||
|
||||
void EmitCompositeExtractF32x3(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitCompositeExtractF32x3(EmitContext& ctx, Id composite, u32 index) {
|
||||
return ctx.OpCompositeExtract(ctx.F32[1], composite, index);
|
||||
}
|
||||
|
||||
void EmitCompositeExtractF32x4(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitCompositeExtractF32x4(EmitContext& ctx, Id composite, u32 index) {
|
||||
return ctx.OpCompositeExtract(ctx.F32[1], composite, index);
|
||||
}
|
||||
|
||||
void EmitCompositeConstructF64x2(EmitContext&) {
|
||||
|
@ -11,7 +11,7 @@ void EmitBranch(EmitContext& ctx, IR::Block* label) {
|
||||
}
|
||||
|
||||
void EmitBranchConditional(EmitContext& ctx, Id condition, IR::Block* true_label,
|
||||
IR::Block* false_label) {
|
||||
IR::Block* false_label) {
|
||||
ctx.OpBranchConditional(condition, true_label->Definition<Id>(), false_label->Definition<Id>());
|
||||
}
|
||||
|
||||
|
89
src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp
Normal file
89
src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp
Normal file
@ -0,0 +1,89 @@
|
||||
// Copyright 2021 yuzu Emulator Project
|
||||
// Licensed under GPLv2 or any later version
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#include "shader_recompiler/backend/spirv/emit_spirv.h"
|
||||
|
||||
namespace Shader::Backend::SPIRV {
|
||||
|
||||
Id EmitConvertS16F16(EmitContext& ctx, Id value) {
|
||||
return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToS(ctx.U16, value));
|
||||
}
|
||||
|
||||
Id EmitConvertS16F32(EmitContext& ctx, Id value) {
|
||||
return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToS(ctx.U16, value));
|
||||
}
|
||||
|
||||
Id EmitConvertS16F64(EmitContext& ctx, Id value) {
|
||||
return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToS(ctx.U16, value));
|
||||
}
|
||||
|
||||
Id EmitConvertS32F16(EmitContext& ctx, Id value) {
|
||||
return ctx.OpConvertFToS(ctx.U32[1], value);
|
||||
}
|
||||
|
||||
Id EmitConvertS32F32(EmitContext& ctx, Id value) {
|
||||
return ctx.OpConvertFToS(ctx.U32[1], value);
|
||||
}
|
||||
|
||||
Id EmitConvertS32F64(EmitContext& ctx, Id value) {
|
||||
return ctx.OpConvertFToS(ctx.U32[1], value);
|
||||
}
|
||||
|
||||
Id EmitConvertS64F16(EmitContext& ctx, Id value) {
|
||||
return ctx.OpConvertFToS(ctx.U64, value);
|
||||
}
|
||||
|
||||
Id EmitConvertS64F32(EmitContext& ctx, Id value) {
|
||||
return ctx.OpConvertFToS(ctx.U64, value);
|
||||
}
|
||||
|
||||
Id EmitConvertS64F64(EmitContext& ctx, Id value) {
|
||||
return ctx.OpConvertFToS(ctx.U64, value);
|
||||
}
|
||||
|
||||
Id EmitConvertU16F16(EmitContext& ctx, Id value) {
|
||||
return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToU(ctx.U16, value));
|
||||
}
|
||||
|
||||
Id EmitConvertU16F32(EmitContext& ctx, Id value) {
|
||||
return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToU(ctx.U16, value));
|
||||
}
|
||||
|
||||
Id EmitConvertU16F64(EmitContext& ctx, Id value) {
|
||||
return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToU(ctx.U16, value));
|
||||
}
|
||||
|
||||
Id EmitConvertU32F16(EmitContext& ctx, Id value) {
|
||||
return ctx.OpConvertFToU(ctx.U32[1], value);
|
||||
}
|
||||
|
||||
Id EmitConvertU32F32(EmitContext& ctx, Id value) {
|
||||
return ctx.OpConvertFToU(ctx.U32[1], value);
|
||||
}
|
||||
|
||||
Id EmitConvertU32F64(EmitContext& ctx, Id value) {
|
||||
return ctx.OpConvertFToU(ctx.U32[1], value);
|
||||
}
|
||||
|
||||
Id EmitConvertU64F16(EmitContext& ctx, Id value) {
|
||||
return ctx.OpConvertFToU(ctx.U64, value);
|
||||
}
|
||||
|
||||
Id EmitConvertU64F32(EmitContext& ctx, Id value) {
|
||||
return ctx.OpConvertFToU(ctx.U64, value);
|
||||
}
|
||||
|
||||
Id EmitConvertU64F64(EmitContext& ctx, Id value) {
|
||||
return ctx.OpConvertFToU(ctx.U64, value);
|
||||
}
|
||||
|
||||
Id EmitConvertU64U32(EmitContext& ctx, Id value) {
|
||||
return ctx.OpUConvert(ctx.U64, value);
|
||||
}
|
||||
|
||||
Id EmitConvertU32U64(EmitContext& ctx, Id value) {
|
||||
return ctx.OpUConvert(ctx.U32[1], value);
|
||||
}
|
||||
|
||||
} // namespace Shader::Backend::SPIRV
|
@ -169,52 +169,52 @@ void EmitFPSaturate64(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitFPRoundEven16(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitFPRoundEven16(EmitContext& ctx, Id value) {
|
||||
return ctx.OpRoundEven(ctx.F16[1], value);
|
||||
}
|
||||
|
||||
void EmitFPRoundEven32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitFPRoundEven32(EmitContext& ctx, Id value) {
|
||||
return ctx.OpRoundEven(ctx.F32[1], value);
|
||||
}
|
||||
|
||||
void EmitFPRoundEven64(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitFPRoundEven64(EmitContext& ctx, Id value) {
|
||||
return ctx.OpRoundEven(ctx.F64[1], value);
|
||||
}
|
||||
|
||||
void EmitFPFloor16(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitFPFloor16(EmitContext& ctx, Id value) {
|
||||
return ctx.OpFloor(ctx.F16[1], value);
|
||||
}
|
||||
|
||||
void EmitFPFloor32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitFPFloor32(EmitContext& ctx, Id value) {
|
||||
return ctx.OpFloor(ctx.F32[1], value);
|
||||
}
|
||||
|
||||
void EmitFPFloor64(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitFPFloor64(EmitContext& ctx, Id value) {
|
||||
return ctx.OpFloor(ctx.F64[1], value);
|
||||
}
|
||||
|
||||
void EmitFPCeil16(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitFPCeil16(EmitContext& ctx, Id value) {
|
||||
return ctx.OpCeil(ctx.F16[1], value);
|
||||
}
|
||||
|
||||
void EmitFPCeil32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitFPCeil32(EmitContext& ctx, Id value) {
|
||||
return ctx.OpCeil(ctx.F32[1], value);
|
||||
}
|
||||
|
||||
void EmitFPCeil64(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitFPCeil64(EmitContext& ctx, Id value) {
|
||||
return ctx.OpCeil(ctx.F64[1], value);
|
||||
}
|
||||
|
||||
void EmitFPTrunc16(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitFPTrunc16(EmitContext& ctx, Id value) {
|
||||
return ctx.OpTrunc(ctx.F16[1], value);
|
||||
}
|
||||
|
||||
void EmitFPTrunc32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitFPTrunc32(EmitContext& ctx, Id value) {
|
||||
return ctx.OpTrunc(ctx.F32[1], value);
|
||||
}
|
||||
|
||||
void EmitFPTrunc64(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
Id EmitFPTrunc64(EmitContext& ctx, Id value) {
|
||||
return ctx.OpTrunc(ctx.F64[1], value);
|
||||
}
|
||||
|
||||
} // namespace Shader::Backend::SPIRV
|
||||
|
@ -113,20 +113,4 @@ Id EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
|
||||
return ctx.OpUGreaterThanEqual(ctx.U1, lhs, rhs);
|
||||
}
|
||||
|
||||
void EmitLogicalOr(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitLogicalAnd(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitLogicalXor(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitLogicalNot(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
} // namespace Shader::Backend::SPIRV
|
||||
|
@ -6,83 +6,19 @@
|
||||
|
||||
namespace Shader::Backend::SPIRV {
|
||||
|
||||
void EmitConvertS16F16(EmitContext&) {
|
||||
void EmitLogicalOr(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertS16F32(EmitContext&) {
|
||||
void EmitLogicalAnd(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertS16F64(EmitContext&) {
|
||||
void EmitLogicalXor(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertS32F16(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertS32F32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertS32F64(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertS64F16(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertS64F32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertS64F64(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertU16F16(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertU16F32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertU16F64(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertU32F16(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertU32F32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertU32F64(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertU64F16(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertU64F32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertU64F64(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertU64U32(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitConvertU32U64(EmitContext&) {
|
||||
void EmitLogicalNot(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
|
@ -94,8 +94,7 @@ void EmitLoadStorageS16(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
Id EmitLoadStorage32(EmitContext& ctx, const IR::Value& binding,
|
||||
const IR::Value& offset) {
|
||||
Id EmitLoadStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
|
||||
if (!binding.IsImmediate()) {
|
||||
throw NotImplementedException("Dynamic storage buffer indexing");
|
||||
}
|
||||
@ -129,8 +128,8 @@ void EmitWriteStorageS16(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
}
|
||||
|
||||
void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding,
|
||||
const IR::Value& offset, Id value) {
|
||||
void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value) {
|
||||
if (!binding.IsImmediate()) {
|
||||
throw NotImplementedException("Dynamic storage buffer indexing");
|
||||
}
|
||||
@ -140,8 +139,19 @@ void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding,
|
||||
ctx.OpStore(pointer, value);
|
||||
}
|
||||
|
||||
void EmitWriteStorage64(EmitContext&) {
|
||||
throw NotImplementedException("SPIR-V Instruction");
|
||||
void EmitWriteStorage64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
||||
Id value) {
|
||||
if (!binding.IsImmediate()) {
|
||||
throw NotImplementedException("Dynamic storage buffer indexing");
|
||||
}
|
||||
// TODO: Support reinterpreting bindings, guaranteed to be aligned
|
||||
const Id ssbo{ctx.ssbos[binding.U32()]};
|
||||
const Id low_index{StorageIndex(ctx, offset, sizeof(u32))};
|
||||
const Id high_index{ctx.OpIAdd(ctx.U32[1], low_index, ctx.Constant(ctx.U32[1], 1U))};
|
||||
const Id low_pointer{ctx.OpAccessChain(ctx.storage_u32, ssbo, ctx.u32_zero_value, low_index)};
|
||||
const Id high_pointer{ctx.OpAccessChain(ctx.storage_u32, ssbo, ctx.u32_zero_value, high_index)};
|
||||
ctx.OpStore(low_pointer, ctx.OpCompositeExtract(ctx.U32[1], value, 0U));
|
||||
ctx.OpStore(high_pointer, ctx.OpCompositeExtract(ctx.U32[1], value, 1U));
|
||||
}
|
||||
|
||||
void EmitWriteStorage128(EmitContext&) {
|
||||
|
@ -4,8 +4,8 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <string>
|
||||
#include <compare>
|
||||
#include <string>
|
||||
|
||||
#include <fmt/format.h>
|
||||
|
||||
|
@ -547,11 +547,11 @@ F32 IREmitter::FPSqrt(const F32& value) {
|
||||
|
||||
F16F32F64 IREmitter::FPSaturate(const F16F32F64& value) {
|
||||
switch (value.Type()) {
|
||||
case Type::U16:
|
||||
case Type::F16:
|
||||
return Inst<F16>(Opcode::FPSaturate16, value);
|
||||
case Type::U32:
|
||||
case Type::F32:
|
||||
return Inst<F32>(Opcode::FPSaturate32, value);
|
||||
case Type::U64:
|
||||
case Type::F64:
|
||||
return Inst<F64>(Opcode::FPSaturate64, value);
|
||||
default:
|
||||
ThrowInvalidType(value.Type());
|
||||
@ -560,11 +560,11 @@ F16F32F64 IREmitter::FPSaturate(const F16F32F64& value) {
|
||||
|
||||
F16F32F64 IREmitter::FPRoundEven(const F16F32F64& value) {
|
||||
switch (value.Type()) {
|
||||
case Type::U16:
|
||||
case Type::F16:
|
||||
return Inst<F16>(Opcode::FPRoundEven16, value);
|
||||
case Type::U32:
|
||||
case Type::F32:
|
||||
return Inst<F32>(Opcode::FPRoundEven32, value);
|
||||
case Type::U64:
|
||||
case Type::F64:
|
||||
return Inst<F64>(Opcode::FPRoundEven64, value);
|
||||
default:
|
||||
ThrowInvalidType(value.Type());
|
||||
@ -573,11 +573,11 @@ F16F32F64 IREmitter::FPRoundEven(const F16F32F64& value) {
|
||||
|
||||
F16F32F64 IREmitter::FPFloor(const F16F32F64& value) {
|
||||
switch (value.Type()) {
|
||||
case Type::U16:
|
||||
case Type::F16:
|
||||
return Inst<F16>(Opcode::FPFloor16, value);
|
||||
case Type::U32:
|
||||
case Type::F32:
|
||||
return Inst<F32>(Opcode::FPFloor32, value);
|
||||
case Type::U64:
|
||||
case Type::F64:
|
||||
return Inst<F64>(Opcode::FPFloor64, value);
|
||||
default:
|
||||
ThrowInvalidType(value.Type());
|
||||
@ -586,11 +586,11 @@ F16F32F64 IREmitter::FPFloor(const F16F32F64& value) {
|
||||
|
||||
F16F32F64 IREmitter::FPCeil(const F16F32F64& value) {
|
||||
switch (value.Type()) {
|
||||
case Type::U16:
|
||||
case Type::F16:
|
||||
return Inst<F16>(Opcode::FPCeil16, value);
|
||||
case Type::U32:
|
||||
case Type::F32:
|
||||
return Inst<F32>(Opcode::FPCeil32, value);
|
||||
case Type::U64:
|
||||
case Type::F64:
|
||||
return Inst<F64>(Opcode::FPCeil64, value);
|
||||
default:
|
||||
ThrowInvalidType(value.Type());
|
||||
@ -599,11 +599,11 @@ F16F32F64 IREmitter::FPCeil(const F16F32F64& value) {
|
||||
|
||||
F16F32F64 IREmitter::FPTrunc(const F16F32F64& value) {
|
||||
switch (value.Type()) {
|
||||
case Type::U16:
|
||||
case Type::F16:
|
||||
return Inst<F16>(Opcode::FPTrunc16, value);
|
||||
case Type::U32:
|
||||
case Type::F32:
|
||||
return Inst<F32>(Opcode::FPTrunc32, value);
|
||||
case Type::U64:
|
||||
case Type::F64:
|
||||
return Inst<F64>(Opcode::FPTrunc64, value);
|
||||
default:
|
||||
ThrowInvalidType(value.Type());
|
||||
@ -729,33 +729,33 @@ U32U64 IREmitter::ConvertFToS(size_t bitsize, const F16F32F64& value) {
|
||||
switch (bitsize) {
|
||||
case 16:
|
||||
switch (value.Type()) {
|
||||
case Type::U16:
|
||||
case Type::F16:
|
||||
return Inst<U32>(Opcode::ConvertS16F16, value);
|
||||
case Type::U32:
|
||||
case Type::F32:
|
||||
return Inst<U32>(Opcode::ConvertS16F32, value);
|
||||
case Type::U64:
|
||||
case Type::F64:
|
||||
return Inst<U32>(Opcode::ConvertS16F64, value);
|
||||
default:
|
||||
ThrowInvalidType(value.Type());
|
||||
}
|
||||
case 32:
|
||||
switch (value.Type()) {
|
||||
case Type::U16:
|
||||
case Type::F16:
|
||||
return Inst<U32>(Opcode::ConvertS32F16, value);
|
||||
case Type::U32:
|
||||
case Type::F32:
|
||||
return Inst<U32>(Opcode::ConvertS32F32, value);
|
||||
case Type::U64:
|
||||
case Type::F64:
|
||||
return Inst<U32>(Opcode::ConvertS32F64, value);
|
||||
default:
|
||||
ThrowInvalidType(value.Type());
|
||||
}
|
||||
case 64:
|
||||
switch (value.Type()) {
|
||||
case Type::U16:
|
||||
case Type::F16:
|
||||
return Inst<U64>(Opcode::ConvertS64F16, value);
|
||||
case Type::U32:
|
||||
case Type::F32:
|
||||
return Inst<U64>(Opcode::ConvertS64F32, value);
|
||||
case Type::U64:
|
||||
case Type::F64:
|
||||
return Inst<U64>(Opcode::ConvertS64F64, value);
|
||||
default:
|
||||
ThrowInvalidType(value.Type());
|
||||
@ -769,33 +769,33 @@ U32U64 IREmitter::ConvertFToU(size_t bitsize, const F16F32F64& value) {
|
||||
switch (bitsize) {
|
||||
case 16:
|
||||
switch (value.Type()) {
|
||||
case Type::U16:
|
||||
case Type::F16:
|
||||
return Inst<U32>(Opcode::ConvertU16F16, value);
|
||||
case Type::U32:
|
||||
case Type::F32:
|
||||
return Inst<U32>(Opcode::ConvertU16F32, value);
|
||||
case Type::U64:
|
||||
case Type::F64:
|
||||
return Inst<U32>(Opcode::ConvertU16F64, value);
|
||||
default:
|
||||
ThrowInvalidType(value.Type());
|
||||
}
|
||||
case 32:
|
||||
switch (value.Type()) {
|
||||
case Type::U16:
|
||||
case Type::F16:
|
||||
return Inst<U32>(Opcode::ConvertU32F16, value);
|
||||
case Type::U32:
|
||||
case Type::F32:
|
||||
return Inst<U32>(Opcode::ConvertU32F32, value);
|
||||
case Type::U64:
|
||||
case Type::F64:
|
||||
return Inst<U32>(Opcode::ConvertU32F64, value);
|
||||
default:
|
||||
ThrowInvalidType(value.Type());
|
||||
}
|
||||
case 64:
|
||||
switch (value.Type()) {
|
||||
case Type::U16:
|
||||
case Type::F16:
|
||||
return Inst<U64>(Opcode::ConvertU64F16, value);
|
||||
case Type::U32:
|
||||
case Type::F32:
|
||||
return Inst<U64>(Opcode::ConvertU64F32, value);
|
||||
case Type::U64:
|
||||
case Type::F64:
|
||||
return Inst<U64>(Opcode::ConvertU64F64, value);
|
||||
default:
|
||||
ThrowInvalidType(value.Type());
|
||||
@ -829,10 +829,10 @@ U32U64 IREmitter::ConvertU(size_t result_bitsize, const U32U64& value) {
|
||||
case 64:
|
||||
switch (value.Type()) {
|
||||
case Type::U32:
|
||||
return Inst<U64>(Opcode::ConvertU64U32, value);
|
||||
case Type::U64:
|
||||
// Nothing to do
|
||||
return value;
|
||||
case Type::U64:
|
||||
return Inst<U64>(Opcode::ConvertU64U32, value);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
@ -216,6 +216,10 @@ void Inst::ReplaceUsesWith(Value replacement) {
|
||||
}
|
||||
}
|
||||
|
||||
void Inst::ReplaceOpcode(IR::Opcode opcode) {
|
||||
op = opcode;
|
||||
}
|
||||
|
||||
void Inst::Use(const Value& value) {
|
||||
Inst* const inst{value.Inst()};
|
||||
++inst->use_count;
|
||||
|
@ -86,6 +86,8 @@ public:
|
||||
|
||||
void ReplaceUsesWith(Value replacement);
|
||||
|
||||
void ReplaceOpcode(IR::Opcode opcode);
|
||||
|
||||
template <typename FlagsType>
|
||||
requires(sizeof(FlagsType) <= sizeof(u32) && std::is_trivially_copyable_v<FlagsType>)
|
||||
[[nodiscard]] FlagsType Flags() const noexcept {
|
||||
|
@ -119,8 +119,10 @@ OPCODE(PackUint2x32, U64, U32x
|
||||
OPCODE(UnpackUint2x32, U32x2, U64, )
|
||||
OPCODE(PackFloat2x16, U32, F16x2, )
|
||||
OPCODE(UnpackFloat2x16, F16x2, U32, )
|
||||
OPCODE(PackDouble2x32, U64, U32x2, )
|
||||
OPCODE(UnpackDouble2x32, U32x2, U64, )
|
||||
OPCODE(PackHalf2x16, U32, F32x2, )
|
||||
OPCODE(UnpackHalf2x16, F32x2, U32, )
|
||||
OPCODE(PackDouble2x32, F64, U32x2, )
|
||||
OPCODE(UnpackDouble2x32, U32x2, F64, )
|
||||
|
||||
// Pseudo-operation, handled specially at final emit
|
||||
OPCODE(GetZeroFromOp, U1, Opaque, )
|
||||
|
@ -35,4 +35,4 @@ std::string DumpProgram(const Program& program) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
} // namespace Shader::IR
|
||||
} // namespace Shader::IR
|
||||
|
@ -56,6 +56,7 @@ IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Blo
|
||||
.post_order_blocks{},
|
||||
});
|
||||
}
|
||||
Optimization::LowerFp16ToFp32(program);
|
||||
for (IR::Function& function : functions) {
|
||||
function.post_order_blocks = PostOrder(function.blocks);
|
||||
Optimization::SsaRewritePass(function.post_order_blocks);
|
||||
@ -69,6 +70,7 @@ IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Blo
|
||||
Optimization::VerificationPass(function);
|
||||
}
|
||||
Optimization::CollectShaderInfoPass(program);
|
||||
|
||||
fmt::print(stdout, "{}\n", IR::DumpProgram(program));
|
||||
return program;
|
||||
}
|
||||
|
@ -34,7 +34,7 @@ union F2I {
|
||||
BitField<8, 2, DestFormat> dest_format;
|
||||
BitField<10, 2, SrcFormat> src_format;
|
||||
BitField<12, 1, u64> is_signed;
|
||||
BitField<39, 1, Rounding> rounding;
|
||||
BitField<39, 2, Rounding> rounding;
|
||||
BitField<49, 1, u64> half;
|
||||
BitField<44, 1, u64> ftz;
|
||||
BitField<45, 1, u64> abs;
|
||||
@ -55,6 +55,28 @@ size_t BitSize(DestFormat dest_format) {
|
||||
}
|
||||
}
|
||||
|
||||
IR::F64 UnpackCbuf(TranslatorVisitor& v, u64 insn) {
|
||||
union {
|
||||
u64 raw;
|
||||
BitField<20, 14, s64> offset;
|
||||
BitField<34, 5, u64> binding;
|
||||
} const cbuf{insn};
|
||||
if (cbuf.binding >= 18) {
|
||||
throw NotImplementedException("Out of bounds constant buffer binding {}", cbuf.binding);
|
||||
}
|
||||
if (cbuf.offset >= 0x4'000 || cbuf.offset < 0) {
|
||||
throw NotImplementedException("Out of bounds constant buffer offset {}", cbuf.offset * 4);
|
||||
}
|
||||
if (cbuf.offset % 2 != 0) {
|
||||
throw NotImplementedException("Unaligned F64 constant buffer offset {}", cbuf.offset * 4);
|
||||
}
|
||||
const IR::U32 binding{v.ir.Imm32(static_cast<u32>(cbuf.binding))};
|
||||
const IR::U32 byte_offset{v.ir.Imm32(static_cast<u32>(cbuf.offset) * 4 + 4)};
|
||||
const IR::U32 cbuf_data{v.ir.GetCbuf(binding, byte_offset)};
|
||||
const IR::Value vector{v.ir.CompositeConstruct(v.ir.Imm32(0U), cbuf_data)};
|
||||
return v.ir.PackDouble2x32(vector);
|
||||
}
|
||||
|
||||
void TranslateF2I(TranslatorVisitor& v, u64 insn, const IR::F16F32F64& src_a) {
|
||||
// F2I is used to convert from a floating point value to an integer
|
||||
const F2I f2i{insn};
|
||||
@ -82,19 +104,16 @@ void TranslateF2I(TranslatorVisitor& v, u64 insn, const IR::F16F32F64& src_a) {
|
||||
const size_t bitsize{BitSize(f2i.dest_format)};
|
||||
const IR::U16U32U64 result{v.ir.ConvertFToI(bitsize, is_signed, rounded_value)};
|
||||
|
||||
v.X(f2i.dest_reg, result);
|
||||
if (bitsize == 64) {
|
||||
const IR::Value vector{v.ir.UnpackUint2x32(result)};
|
||||
v.X(f2i.dest_reg + 0, IR::U32{v.ir.CompositeExtract(vector, 0)});
|
||||
v.X(f2i.dest_reg + 1, IR::U32{v.ir.CompositeExtract(vector, 1)});
|
||||
} else {
|
||||
v.X(f2i.dest_reg, result);
|
||||
}
|
||||
|
||||
if (f2i.cc != 0) {
|
||||
v.SetZFlag(v.ir.GetZeroFromOp(result));
|
||||
if (is_signed) {
|
||||
v.SetSFlag(v.ir.GetSignFromOp(result));
|
||||
} else {
|
||||
v.ResetSFlag();
|
||||
}
|
||||
v.ResetCFlag();
|
||||
|
||||
// TODO: Investigate if out of bound conversions sets the overflow flag
|
||||
v.ResetOFlag();
|
||||
throw NotImplementedException("F2I CC");
|
||||
}
|
||||
}
|
||||
} // Anonymous namespace
|
||||
@ -118,12 +137,25 @@ void TranslatorVisitor::F2I_reg(u64 insn) {
|
||||
f2i.base.src_format.Value());
|
||||
}
|
||||
}()};
|
||||
|
||||
TranslateF2I(*this, insn, op_a);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::F2I_cbuf(u64) {
|
||||
throw NotImplementedException("{}", Opcode::F2I_cbuf);
|
||||
void TranslatorVisitor::F2I_cbuf(u64 insn) {
|
||||
const F2I f2i{insn};
|
||||
const IR::F16F32F64 op_a{[&]() -> IR::F16F32F64 {
|
||||
switch (f2i.src_format) {
|
||||
case SrcFormat::F16:
|
||||
return IR::F16{ir.CompositeExtract(ir.UnpackFloat2x16(GetCbuf(insn)), f2i.half)};
|
||||
case SrcFormat::F32:
|
||||
return GetCbufF(insn);
|
||||
case SrcFormat::F64: {
|
||||
return UnpackCbuf(*this, insn);
|
||||
}
|
||||
default:
|
||||
throw NotImplementedException("Invalid F2I source format {}", f2i.src_format.Value());
|
||||
}
|
||||
}()};
|
||||
TranslateF2I(*this, insn, op_a);
|
||||
}
|
||||
|
||||
void TranslatorVisitor::F2I_imm(u64) {
|
||||
|
@ -11,7 +11,7 @@ namespace Shader::Maxwell {
|
||||
|
||||
class TranslatorVisitor {
|
||||
public:
|
||||
explicit TranslatorVisitor(Environment& env_, IR::Block& block) : env{env_} ,ir(block) {}
|
||||
explicit TranslatorVisitor(Environment& env_, IR::Block& block) : env{env_}, ir(block) {}
|
||||
|
||||
Environment& env;
|
||||
IR::IREmitter ir;
|
||||
|
@ -26,6 +26,22 @@ void Visit(Info& info, IR::Inst& inst) {
|
||||
case IR::Opcode::LocalInvocationId:
|
||||
info.uses_local_invocation_id = true;
|
||||
break;
|
||||
case IR::Opcode::CompositeConstructF16x2:
|
||||
case IR::Opcode::CompositeConstructF16x3:
|
||||
case IR::Opcode::CompositeConstructF16x4:
|
||||
case IR::Opcode::CompositeExtractF16x2:
|
||||
case IR::Opcode::CompositeExtractF16x3:
|
||||
case IR::Opcode::CompositeExtractF16x4:
|
||||
case IR::Opcode::BitCastU16F16:
|
||||
case IR::Opcode::BitCastF16U16:
|
||||
case IR::Opcode::PackFloat2x16:
|
||||
case IR::Opcode::UnpackFloat2x16:
|
||||
case IR::Opcode::ConvertS16F16:
|
||||
case IR::Opcode::ConvertS32F16:
|
||||
case IR::Opcode::ConvertS64F16:
|
||||
case IR::Opcode::ConvertU16F16:
|
||||
case IR::Opcode::ConvertU32F16:
|
||||
case IR::Opcode::ConvertU64F16:
|
||||
case IR::Opcode::FPAbs16:
|
||||
case IR::Opcode::FPAdd16:
|
||||
case IR::Opcode::FPCeil16:
|
||||
@ -36,7 +52,7 @@ void Visit(Info& info, IR::Inst& inst) {
|
||||
case IR::Opcode::FPRoundEven16:
|
||||
case IR::Opcode::FPSaturate16:
|
||||
case IR::Opcode::FPTrunc16:
|
||||
info.uses_fp16;
|
||||
info.uses_fp16 = true;
|
||||
break;
|
||||
case IR::Opcode::FPAbs64:
|
||||
case IR::Opcode::FPAdd64:
|
||||
|
@ -104,12 +104,12 @@ void FoldGetPred(IR::Inst& inst) {
|
||||
bool FoldXmadMultiply(IR::Block& block, IR::Inst& inst) {
|
||||
/*
|
||||
* We are looking for this pattern:
|
||||
* %rhs_bfe = BitFieldUExtract %factor_a, #0, #16 (uses: 1)
|
||||
* %rhs_mul = IMul32 %rhs_bfe, %factor_b (uses: 1)
|
||||
* %lhs_bfe = BitFieldUExtract %factor_a, #16, #16 (uses: 1)
|
||||
* %rhs_mul = IMul32 %lhs_bfe, %factor_b (uses: 1)
|
||||
* %lhs_shl = ShiftLeftLogical32 %rhs_mul, #16 (uses: 1)
|
||||
* %result = IAdd32 %lhs_shl, %rhs_mul (uses: 10)
|
||||
* %rhs_bfe = BitFieldUExtract %factor_a, #0, #16
|
||||
* %rhs_mul = IMul32 %rhs_bfe, %factor_b
|
||||
* %lhs_bfe = BitFieldUExtract %factor_a, #16, #16
|
||||
* %rhs_mul = IMul32 %lhs_bfe, %factor_b
|
||||
* %lhs_shl = ShiftLeftLogical32 %rhs_mul, #16
|
||||
* %result = IAdd32 %lhs_shl, %rhs_mul
|
||||
*
|
||||
* And replacing it with
|
||||
* %result = IMul32 %factor_a, %factor_b
|
||||
|
79
src/shader_recompiler/ir_opt/lower_fp16_to_fp32.cpp
Normal file
79
src/shader_recompiler/ir_opt/lower_fp16_to_fp32.cpp
Normal file
@ -0,0 +1,79 @@
|
||||
// Copyright 2021 yuzu Emulator Project
|
||||
// Licensed under GPLv2 or any later version
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#include <algorithm>
|
||||
|
||||
#include "shader_recompiler/frontend/ir/ir_emitter.h"
|
||||
#include "shader_recompiler/frontend/ir/microinstruction.h"
|
||||
#include "shader_recompiler/ir_opt/passes.h"
|
||||
|
||||
namespace Shader::Optimization {
|
||||
namespace {
|
||||
IR::Opcode Replace(IR::Opcode op) {
|
||||
switch (op) {
|
||||
case IR::Opcode::FPAbs16:
|
||||
return IR::Opcode::FPAbs32;
|
||||
case IR::Opcode::FPAdd16:
|
||||
return IR::Opcode::FPAdd32;
|
||||
case IR::Opcode::FPCeil16:
|
||||
return IR::Opcode::FPCeil32;
|
||||
case IR::Opcode::FPFloor16:
|
||||
return IR::Opcode::FPFloor32;
|
||||
case IR::Opcode::FPFma16:
|
||||
return IR::Opcode::FPFma32;
|
||||
case IR::Opcode::FPMul16:
|
||||
return IR::Opcode::FPMul32;
|
||||
case IR::Opcode::FPNeg16:
|
||||
return IR::Opcode::FPNeg32;
|
||||
case IR::Opcode::FPRoundEven16:
|
||||
return IR::Opcode::FPRoundEven32;
|
||||
case IR::Opcode::FPSaturate16:
|
||||
return IR::Opcode::FPSaturate32;
|
||||
case IR::Opcode::FPTrunc16:
|
||||
return IR::Opcode::FPTrunc32;
|
||||
case IR::Opcode::CompositeConstructF16x2:
|
||||
return IR::Opcode::CompositeConstructF32x2;
|
||||
case IR::Opcode::CompositeConstructF16x3:
|
||||
return IR::Opcode::CompositeConstructF32x3;
|
||||
case IR::Opcode::CompositeConstructF16x4:
|
||||
return IR::Opcode::CompositeConstructF32x4;
|
||||
case IR::Opcode::CompositeExtractF16x2:
|
||||
return IR::Opcode::CompositeExtractF32x2;
|
||||
case IR::Opcode::CompositeExtractF16x3:
|
||||
return IR::Opcode::CompositeExtractF32x3;
|
||||
case IR::Opcode::CompositeExtractF16x4:
|
||||
return IR::Opcode::CompositeExtractF32x4;
|
||||
case IR::Opcode::ConvertS16F16:
|
||||
return IR::Opcode::ConvertS16F32;
|
||||
case IR::Opcode::ConvertS32F16:
|
||||
return IR::Opcode::ConvertS32F32;
|
||||
case IR::Opcode::ConvertS64F16:
|
||||
return IR::Opcode::ConvertS64F32;
|
||||
case IR::Opcode::ConvertU16F16:
|
||||
return IR::Opcode::ConvertU16F32;
|
||||
case IR::Opcode::ConvertU32F16:
|
||||
return IR::Opcode::ConvertU32F32;
|
||||
case IR::Opcode::ConvertU64F16:
|
||||
return IR::Opcode::ConvertU64F32;
|
||||
case IR::Opcode::PackFloat2x16:
|
||||
return IR::Opcode::PackHalf2x16;
|
||||
case IR::Opcode::UnpackFloat2x16:
|
||||
return IR::Opcode::UnpackHalf2x16;
|
||||
default:
|
||||
return op;
|
||||
}
|
||||
}
|
||||
} // Anonymous namespace
|
||||
|
||||
void LowerFp16ToFp32(IR::Program& program) {
|
||||
for (IR::Function& function : program.functions) {
|
||||
for (IR::Block* const block : function.blocks) {
|
||||
for (IR::Inst& inst : block->Instructions()) {
|
||||
inst.ReplaceOpcode(Replace(inst.Opcode()));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace Shader::Optimization
|
@ -24,6 +24,7 @@ void ConstantPropagationPass(IR::Block& block);
|
||||
void DeadCodeEliminationPass(IR::Block& block);
|
||||
void GlobalMemoryToStorageBufferPass(IR::Program& program);
|
||||
void IdentityRemovalPass(IR::Function& function);
|
||||
void LowerFp16ToFp32(IR::Program& program);
|
||||
void SsaRewritePass(std::span<IR::Block* const> post_order_blocks);
|
||||
void VerificationPass(const IR::Function& function);
|
||||
|
||||
|
@ -67,8 +67,8 @@ int main() {
|
||||
ObjectPool<IR::Inst> inst_pool;
|
||||
ObjectPool<IR::Block> block_pool;
|
||||
|
||||
FileEnvironment env{"D:\\Shaders\\Database\\Oninaki\\CS8F146B41DB6BD826.bin"};
|
||||
// FileEnvironment env{"D:\\Shaders\\shader.bin"};
|
||||
// FileEnvironment env{"D:\\Shaders\\Database\\Oninaki\\CS8F146B41DB6BD826.bin"};
|
||||
FileEnvironment env{"D:\\Shaders\\shader.bin"};
|
||||
block_pool.ReleaseContents();
|
||||
inst_pool.ReleaseContents();
|
||||
flow_block_pool.ReleaseContents();
|
||||
@ -76,5 +76,9 @@ int main() {
|
||||
fmt::print(stdout, "{}\n", cfg.Dot());
|
||||
IR::Program program{TranslateProgram(inst_pool, block_pool, env, cfg)};
|
||||
fmt::print(stdout, "{}\n", IR::DumpProgram(program));
|
||||
void(Backend::SPIRV::EmitSPIRV(env, program));
|
||||
const std::vector<u32> spirv{Backend::SPIRV::EmitSPIRV(env, program)};
|
||||
std::FILE* const file{std::fopen("D:\\shader.spv", "wb")};
|
||||
std::fwrite(spirv.data(), spirv.size(), sizeof(u32), file);
|
||||
std::fclose(file);
|
||||
std::system("spirv-dis D:\\shader.spv");
|
||||
}
|
||||
|
@ -18,7 +18,7 @@ public:
|
||||
}
|
||||
|
||||
template <typename... Args>
|
||||
requires std::is_constructible_v<T, Args...> [[nodiscard]] T* Create(Args&&... args) {
|
||||
requires std::is_constructible_v<T, Args...>[[nodiscard]] T* Create(Args&&... args) {
|
||||
return std::construct_at(Memory(), std::forward<Args>(args)...);
|
||||
}
|
||||
|
||||
|
@ -206,6 +206,8 @@ VKComputePass::VKComputePass(const Device& device, VKDescriptorPool& descriptor_
|
||||
.codeSize = static_cast<u32>(code.size_bytes()),
|
||||
.pCode = code.data(),
|
||||
});
|
||||
/*
|
||||
FIXME
|
||||
pipeline = device.GetLogical().CreateComputePipeline({
|
||||
.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
|
||||
.pNext = nullptr,
|
||||
@ -224,6 +226,7 @@ VKComputePass::VKComputePass(const Device& device, VKDescriptorPool& descriptor_
|
||||
.basePipelineHandle = nullptr,
|
||||
.basePipelineIndex = 0,
|
||||
});
|
||||
*/
|
||||
}
|
||||
|
||||
VKComputePass::~VKComputePass() = default;
|
||||
|
@ -31,8 +31,6 @@
|
||||
#include "video_core/vulkan_common/vulkan_device.h"
|
||||
#include "video_core/vulkan_common/vulkan_wrapper.h"
|
||||
|
||||
#pragma optimize("", off)
|
||||
|
||||
namespace Vulkan {
|
||||
MICROPROFILE_DECLARE(Vulkan_PipelineCache);
|
||||
|
||||
@ -180,6 +178,12 @@ ComputePipeline PipelineCache::CreateComputePipeline(ShaderInfo* shader_info) {
|
||||
// TODO: Load from cache
|
||||
}
|
||||
const auto [info, code]{Shader::RecompileSPIRV(env, qmd.program_start)};
|
||||
|
||||
FILE* file = fopen("D:\\shader.spv", "wb");
|
||||
fwrite(code.data(), 4, code.size(), file);
|
||||
fclose(file);
|
||||
std::system("spirv-dis D:\\shader.spv");
|
||||
|
||||
shader_info->unique_hash = env.ComputeHash();
|
||||
shader_info->size_bytes = env.ShaderSize();
|
||||
return ComputePipeline{device, descriptor_pool, update_descriptor_queue, info,
|
||||
|
@ -36,8 +36,6 @@
|
||||
#include "video_core/vulkan_common/vulkan_device.h"
|
||||
#include "video_core/vulkan_common/vulkan_wrapper.h"
|
||||
|
||||
#pragma optimize("", off)
|
||||
|
||||
namespace Vulkan {
|
||||
|
||||
using Maxwell = Tegra::Engines::Maxwell3D::Regs;
|
||||
|
@ -247,9 +247,9 @@ Device::Device(VkInstance instance_, vk::PhysicalDevice physical_, VkSurfaceKHR
|
||||
.shaderStorageImageArrayDynamicIndexing = false,
|
||||
.shaderClipDistance = false,
|
||||
.shaderCullDistance = false,
|
||||
.shaderFloat64 = false,
|
||||
.shaderInt64 = false,
|
||||
.shaderInt16 = false,
|
||||
.shaderFloat64 = true,
|
||||
.shaderInt64 = true,
|
||||
.shaderInt16 = true,
|
||||
.shaderResourceResidency = false,
|
||||
.shaderResourceMinLod = false,
|
||||
.sparseBinding = false,
|
||||
@ -420,8 +420,8 @@ Device::Device(VkInstance instance_, vk::PhysicalDevice physical_, VkSurfaceKHR
|
||||
}
|
||||
if (is_float16_supported && driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS) {
|
||||
// Intel's compiler crashes when using fp16 on Astral Chain, disable it for the time being.
|
||||
LOG_WARNING(Render_Vulkan, "Blacklisting Intel proprietary from float16 math");
|
||||
is_float16_supported = false;
|
||||
// LOG_WARNING(Render_Vulkan, "Blacklisting Intel proprietary from float16 math");
|
||||
// is_float16_supported = false;
|
||||
}
|
||||
|
||||
graphics_queue = logical.GetQueue(graphics_family);
|
||||
|
Loading…
Reference in New Issue
Block a user