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Merge pull request #1172 from tech4me/impl_iadd3
Shaders: Implemented IADD3
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commit
6e73039eb5
@ -213,6 +213,18 @@ enum class XmadMode : u64 {
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CBcc = 4,
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CBcc = 4,
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};
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};
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enum class IAdd3Mode : u64 {
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None = 0,
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RightShift = 1,
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LeftShift = 2,
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};
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enum class IAdd3Height : u64 {
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None = 0,
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LowerHalfWord = 1,
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UpperHalfWord = 2,
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};
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enum class FlowCondition : u64 {
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enum class FlowCondition : u64 {
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Always = 0xF,
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Always = 0xF,
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Fcsm_Tr = 0x1C, // TODO(bunnei): What is this used for?
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Fcsm_Tr = 0x1C, // TODO(bunnei): What is this used for?
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@ -338,6 +350,16 @@ union Instruction {
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BitField<48, 1, u64> is_signed;
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BitField<48, 1, u64> is_signed;
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} imnmx;
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} imnmx;
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union {
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BitField<31, 2, IAdd3Height> height_c;
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BitField<33, 2, IAdd3Height> height_b;
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BitField<35, 2, IAdd3Height> height_a;
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BitField<37, 2, IAdd3Mode> mode;
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BitField<49, 1, u64> neg_c;
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BitField<50, 1, u64> neg_b;
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BitField<51, 1, u64> neg_a;
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} iadd3;
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union {
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union {
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BitField<54, 1, u64> saturate;
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BitField<54, 1, u64> saturate;
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BitField<56, 1, u64> negate_a;
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BitField<56, 1, u64> negate_a;
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@ -636,7 +658,7 @@ public:
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IADD_C,
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IADD_C,
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IADD_R,
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IADD_R,
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IADD_IMM,
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IADD_IMM,
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IADD3_C,
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IADD3_C, // Add 3 Integers
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IADD3_R,
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IADD3_R,
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IADD3_IMM,
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IADD3_IMM,
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IADD32I,
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IADD32I,
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@ -1287,6 +1287,67 @@ private:
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instr.alu.saturate_d);
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instr.alu.saturate_d);
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break;
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break;
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}
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}
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case OpCode::Id::IADD3_C:
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case OpCode::Id::IADD3_R:
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case OpCode::Id::IADD3_IMM: {
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std::string op_c = regs.GetRegisterAsInteger(instr.gpr39);
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auto apply_height = [](auto height, auto& oprand) {
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switch (height) {
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case Tegra::Shader::IAdd3Height::None:
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break;
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case Tegra::Shader::IAdd3Height::LowerHalfWord:
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oprand = "((" + oprand + ") & 0xFFFF)";
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break;
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case Tegra::Shader::IAdd3Height::UpperHalfWord:
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oprand = "((" + oprand + ") >> 16)";
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break;
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default:
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LOG_CRITICAL(HW_GPU, "Unhandled IADD3 height: {}",
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static_cast<u32>(height.Value()));
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UNREACHABLE();
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}
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};
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if (opcode->GetId() == OpCode::Id::IADD3_R) {
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apply_height(instr.iadd3.height_a, op_a);
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apply_height(instr.iadd3.height_b, op_b);
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apply_height(instr.iadd3.height_c, op_c);
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}
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if (instr.iadd3.neg_a)
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op_a = "-(" + op_a + ')';
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if (instr.iadd3.neg_b)
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op_b = "-(" + op_b + ')';
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if (instr.iadd3.neg_c)
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op_c = "-(" + op_c + ')';
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std::string result;
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if (opcode->GetId() == OpCode::Id::IADD3_R) {
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switch (instr.iadd3.mode) {
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case Tegra::Shader::IAdd3Mode::RightShift:
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// TODO(tech4me): According to
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// https://envytools.readthedocs.io/en/latest/hw/graph/maxwell/cuda/int.html?highlight=iadd3
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// The addition between op_a and op_b should be done in uint33, more
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// investigation required
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result = "(((" + op_a + " + " + op_b + ") >> 16) + " + op_c + ')';
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break;
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case Tegra::Shader::IAdd3Mode::LeftShift:
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result = "(((" + op_a + " + " + op_b + ") << 16) + " + op_c + ')';
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break;
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default:
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result = '(' + op_a + " + " + op_b + " + " + op_c + ')';
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break;
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}
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} else {
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result = '(' + op_a + " + " + op_b + " + " + op_c + ')';
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}
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regs.SetRegisterToInteger(instr.gpr0, true, 0, result, 1, 1);
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break;
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}
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case OpCode::Id::ISCADD_C:
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case OpCode::Id::ISCADD_C:
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case OpCode::Id::ISCADD_R:
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case OpCode::Id::ISCADD_R:
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case OpCode::Id::ISCADD_IMM: {
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case OpCode::Id::ISCADD_IMM: {
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