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https://github.com/yuzu-emu/yuzu.git
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Merge pull request #344 from bunnei/shader-decompiler-p2
Shader decompiler changes part 2
This commit is contained in:
commit
71b4a3b9f6
@ -192,11 +192,6 @@ private:
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static_assert(position < 8 * sizeof(T), "Invalid position");
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static_assert(bits <= 8 * sizeof(T), "Invalid number of bits");
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static_assert(bits > 0, "Invalid number of bits");
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static_assert(std::is_pod<T>::value, "Invalid base type");
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static_assert(std::is_trivially_copyable_v<T>, "T must be trivially copyable in a BitField");
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};
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#pragma pack()
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#if (__GNUC__ >= 5) || defined(__clang__) || defined(_MSC_VER)
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static_assert(std::is_trivially_copyable<BitField<0, 1, unsigned>>::value,
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"BitField must be trivially copyable");
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#endif
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@ -4,6 +4,7 @@
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#pragma once
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#include <cstring>
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#include <map>
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#include <string>
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#include "common/bit_field.h"
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@ -12,14 +13,10 @@ namespace Tegra {
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namespace Shader {
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struct Register {
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Register() = default;
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constexpr Register() = default;
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constexpr Register(u64 value) : value(value) {}
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constexpr u64 GetIndex() const {
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return value;
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}
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constexpr operator u64() const {
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return value;
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}
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@ -43,13 +40,13 @@ struct Register {
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}
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private:
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u64 value;
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u64 value{};
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};
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union Attribute {
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Attribute() = default;
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constexpr Attribute(u64 value) : value(value) {}
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constexpr explicit Attribute(u64 value) : value(value) {}
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enum class Index : u64 {
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Position = 7,
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@ -68,7 +65,20 @@ union Attribute {
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} fmt28;
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BitField<39, 8, u64> reg;
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u64 value;
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u64 value{};
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};
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union Sampler {
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Sampler() = default;
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constexpr explicit Sampler(u64 value) : value(value) {}
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enum class Index : u64 {
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Sampler_0 = 8,
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};
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BitField<36, 13, Index> index;
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u64 value{};
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};
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union Uniform {
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@ -238,7 +248,7 @@ union OpCode {
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BitField<55, 9, Id> op3;
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BitField<52, 12, Id> op4;
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BitField<51, 13, Id> op5;
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u64 value;
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u64 value{};
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};
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static_assert(sizeof(OpCode) == 0x8, "Incorrect structure size");
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@ -280,6 +290,7 @@ enum class SubOp : u64 {
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Lg2 = 0x3,
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Rcp = 0x4,
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Rsq = 0x5,
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Min = 0x8,
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};
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union Instruction {
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@ -295,15 +306,25 @@ union Instruction {
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BitField<20, 8, Register> gpr20;
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BitField<20, 7, SubOp> sub_op;
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BitField<28, 8, Register> gpr28;
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BitField<36, 13, u64> imm36;
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BitField<39, 8, Register> gpr39;
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union {
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BitField<20, 19, u64> imm20;
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BitField<45, 1, u64> negate_b;
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BitField<46, 1, u64> abs_a;
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BitField<48, 1, u64> negate_a;
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BitField<49, 1, u64> abs_b;
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BitField<50, 1, u64> abs_d;
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BitField<56, 1, u64> negate_imm;
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float GetImm20() const {
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float result{};
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u32 imm{static_cast<u32>(imm20)};
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imm <<= 12;
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imm |= negate_imm ? 0x80000000 : 0;
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std::memcpy(&result, &imm, sizeof(imm));
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return result;
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}
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} alu;
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union {
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@ -311,11 +332,13 @@ union Instruction {
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BitField<49, 1, u64> negate_c;
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} ffma;
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BitField<61, 1, u64> is_b_imm;
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BitField<60, 1, u64> is_b_gpr;
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BitField<59, 1, u64> is_c_gpr;
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Attribute attribute;
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Uniform uniform;
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Sampler sampler;
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u64 hex;
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};
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@ -17,6 +17,7 @@ using Tegra::Shader::Attribute;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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using Tegra::Shader::Sampler;
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using Tegra::Shader::SubOp;
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using Tegra::Shader::Uniform;
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@ -155,23 +156,27 @@ private:
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/// Generates code representing an input attribute register.
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std::string GetInputAttribute(Attribute::Index attribute) {
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declr_input_attribute.insert(attribute);
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switch (attribute) {
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case Attribute::Index::Position:
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return "position";
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default:
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const u32 index{static_cast<u32>(attribute) -
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static_cast<u32>(Attribute::Index::Attribute_0)};
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if (attribute >= Attribute::Index::Attribute_0) {
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declr_input_attribute.insert(attribute);
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return "input_attribute_" + std::to_string(index);
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}
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const u32 index{static_cast<u32>(attribute) -
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static_cast<u32>(Attribute::Index::Attribute_0)};
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if (attribute >= Attribute::Index::Attribute_0) {
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return "input_attribute_" + std::to_string(index);
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NGLOG_CRITICAL(HW_GPU, "Unhandled input attribute: {}", index);
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UNREACHABLE();
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}
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LOG_CRITICAL(HW_GPU, "Unhandled input attribute: 0x%02x", index);
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UNREACHABLE();
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}
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/// Generates code representing an output attribute register.
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std::string GetOutputAttribute(Attribute::Index attribute) {
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switch (attribute) {
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case Attribute::Index::Position:
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return "gl_Position";
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return "position";
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default:
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const u32 index{static_cast<u32>(attribute) -
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static_cast<u32>(Attribute::Index::Attribute_0)};
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@ -180,22 +185,42 @@ private:
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return "output_attribute_" + std::to_string(index);
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}
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LOG_CRITICAL(HW_GPU, "Unhandled output attribute: 0x%02x", index);
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NGLOG_CRITICAL(HW_GPU, "Unhandled output attribute: {}", index);
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UNREACHABLE();
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}
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}
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/// Generates code representing an immediate value
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static std::string GetImmediate(const Instruction& instr) {
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return std::to_string(instr.alu.GetImm20());
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}
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/// Generates code representing a temporary (GPR) register.
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std::string GetRegister(const Register& reg) {
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return *declr_register.insert("register_" + std::to_string(reg)).first;
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std::string GetRegister(const Register& reg, unsigned elem = 0) {
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment && reg < 4) {
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// GPRs 0-3 are output color for the fragment shader
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return std::string{"color."} + "rgba"[(reg + elem) & 3];
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}
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return *declr_register.insert("register_" + std::to_string(reg + elem)).first;
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}
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/// Generates code representing a uniform (C buffer) register.
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std::string GetUniform(const Uniform& reg) {
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declr_const_buffers[reg.index].MarkAsUsed(reg.index, reg.offset, stage);
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declr_const_buffers[reg.index].MarkAsUsed(static_cast<unsigned>(reg.index),
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static_cast<unsigned>(reg.offset), stage);
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return 'c' + std::to_string(reg.index) + '[' + std::to_string(reg.offset) + ']';
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}
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/// Generates code representing a texture sampler.
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std::string GetSampler(const Sampler& sampler) const {
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// TODO(Subv): Support more than just texture sampler 0
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ASSERT_MSG(sampler.index == Sampler::Index::Sampler_0, "unsupported");
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const unsigned index{static_cast<unsigned>(sampler.index.Value()) -
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static_cast<unsigned>(Sampler::Index::Sampler_0)};
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return "tex[" + std::to_string(index) + "]";
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}
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/**
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* Adds code that calls a subroutine.
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* @param subroutine the subroutine to call.
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@ -217,12 +242,13 @@ private:
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* @param value the code representing the value to assign.
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*/
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void SetDest(u64 elem, const std::string& reg, const std::string& value,
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u64 dest_num_components, u64 value_num_components) {
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u64 dest_num_components, u64 value_num_components, bool is_abs = false) {
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std::string swizzle = ".";
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swizzle += "xyzw"[elem];
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std::string dest = reg + (dest_num_components != 1 ? swizzle : "");
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std::string src = "(" + value + ")" + (value_num_components != 1 ? swizzle : "");
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src = is_abs ? "abs(" + src + ")" : src;
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shader.AddLine(dest + " = " + src + ";");
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}
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@ -240,8 +266,6 @@ private:
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switch (OpCode::GetInfo(instr.opcode).type) {
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case OpCode::Type::Arithmetic: {
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ASSERT(!instr.alu.abs_d);
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std::string dest = GetRegister(instr.gpr0);
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std::string op_a = instr.alu.negate_a ? "-" : "";
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op_a += GetRegister(instr.gpr8);
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@ -250,63 +274,109 @@ private:
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}
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std::string op_b = instr.alu.negate_b ? "-" : "";
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if (instr.is_b_gpr) {
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op_b += GetRegister(instr.gpr20);
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if (instr.is_b_imm) {
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op_b += GetImmediate(instr);
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} else {
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op_b += GetUniform(instr.uniform);
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if (instr.is_b_gpr) {
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op_b += GetRegister(instr.gpr20);
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} else {
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op_b += GetUniform(instr.uniform);
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}
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}
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if (instr.alu.abs_b) {
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op_b = "abs(" + op_b + ")";
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}
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switch (instr.opcode.EffectiveOpCode()) {
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case OpCode::Id::FMUL_C:
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case OpCode::Id::FMUL_R: {
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SetDest(0, dest, op_a + " * " + op_b, 1, 1);
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case OpCode::Id::FMUL_R:
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case OpCode::Id::FMUL_IMM: {
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SetDest(0, dest, op_a + " * " + op_b, 1, 1, instr.alu.abs_d);
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break;
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}
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case OpCode::Id::FADD_C:
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case OpCode::Id::FADD_R: {
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SetDest(0, dest, op_a + " + " + op_b, 1, 1);
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case OpCode::Id::FADD_R:
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case OpCode::Id::FADD_IMM: {
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SetDest(0, dest, op_a + " + " + op_b, 1, 1, instr.alu.abs_d);
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break;
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}
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case OpCode::Id::MUFU: {
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switch (instr.sub_op) {
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case SubOp::Cos:
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SetDest(0, dest, "cos(" + op_a + ")", 1, 1, instr.alu.abs_d);
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break;
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case SubOp::Sin:
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SetDest(0, dest, "sin(" + op_a + ")", 1, 1, instr.alu.abs_d);
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break;
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case SubOp::Ex2:
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SetDest(0, dest, "exp2(" + op_a + ")", 1, 1, instr.alu.abs_d);
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break;
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case SubOp::Lg2:
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SetDest(0, dest, "log2(" + op_a + ")", 1, 1, instr.alu.abs_d);
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break;
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case SubOp::Rcp:
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SetDest(0, dest, "1.0 / " + op_a, 1, 1, instr.alu.abs_d);
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break;
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case SubOp::Rsq:
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SetDest(0, dest, "inversesqrt(" + op_a + ")", 1, 1, instr.alu.abs_d);
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break;
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case SubOp::Min:
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SetDest(0, dest, "min(" + op_a + "," + op_b + ")", 1, 1, instr.alu.abs_d);
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break;
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default:
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NGLOG_CRITICAL(HW_GPU, "Unhandled MUFU sub op: {}",
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static_cast<unsigned>(instr.sub_op.Value()));
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UNREACHABLE();
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}
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break;
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}
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default: {
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LOG_CRITICAL(HW_GPU, "Unhandled arithmetic instruction: 0x%02x (%s): 0x%08x",
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static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
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OpCode::GetInfo(instr.opcode).name.c_str(), instr.hex);
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throw DecompileFail("Unhandled instruction");
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break;
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NGLOG_CRITICAL(HW_GPU, "Unhandled arithmetic instruction: {} ({}): {}",
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static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
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OpCode::GetInfo(instr.opcode).name, instr.hex);
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UNREACHABLE();
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}
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}
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break;
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}
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case OpCode::Type::Ffma: {
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ASSERT_MSG(!instr.ffma.negate_b, "untested");
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ASSERT_MSG(!instr.ffma.negate_c, "untested");
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std::string dest = GetRegister(instr.gpr0);
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std::string op_a = GetRegister(instr.gpr8);
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std::string op_b = instr.ffma.negate_b ? "-" : "";
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op_b += GetUniform(instr.uniform);
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std::string op_c = instr.ffma.negate_c ? "-" : "";
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op_c += GetRegister(instr.gpr39);
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switch (instr.opcode.EffectiveOpCode()) {
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case OpCode::Id::FFMA_CR: {
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SetDest(0, dest, op_a + " * " + op_b + " + " + op_c, 1, 1);
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op_b += GetUniform(instr.uniform);
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op_c += GetRegister(instr.gpr39);
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break;
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}
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case OpCode::Id::FFMA_RR: {
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op_b += GetRegister(instr.gpr20);
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op_c += GetRegister(instr.gpr39);
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break;
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}
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case OpCode::Id::FFMA_RC: {
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op_b += GetRegister(instr.gpr39);
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op_c += GetUniform(instr.uniform);
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break;
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}
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case OpCode::Id::FFMA_IMM: {
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op_b += GetImmediate(instr);
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op_c += GetRegister(instr.gpr39);
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break;
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}
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default: {
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NGLOG_CRITICAL(HW_GPU, "Unhandled FFMA instruction: {} ({}): {}",
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static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
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OpCode::GetInfo(instr.opcode).name, instr.hex);
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UNREACHABLE();
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}
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}
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default: {
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LOG_CRITICAL(HW_GPU, "Unhandled arithmetic FFMA instruction: 0x%02x (%s): 0x%08x",
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static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
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OpCode::GetInfo(instr.opcode).name.c_str(), instr.hex);
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throw DecompileFail("Unhandled instruction");
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break;
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}
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}
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SetDest(0, dest, op_a + " * " + op_b + " + " + op_c, 1, 1);
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break;
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}
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case OpCode::Type::Memory: {
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@ -315,22 +385,33 @@ private:
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switch (instr.opcode.EffectiveOpCode()) {
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case OpCode::Id::LD_A: {
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ASSERT(instr.attribute.fmt20.size == 0);
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ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested");
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SetDest(instr.attribute.fmt20.element, gpr0, GetInputAttribute(attribute), 1, 4);
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break;
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}
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case OpCode::Id::ST_A: {
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ASSERT(instr.attribute.fmt20.size == 0);
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ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested");
|
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SetDest(instr.attribute.fmt20.element, GetOutputAttribute(attribute), gpr0, 4, 1);
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break;
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}
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default: {
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LOG_CRITICAL(HW_GPU, "Unhandled memory instruction: 0x%02x (%s): 0x%08x",
|
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static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
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OpCode::GetInfo(instr.opcode).name.c_str(), instr.hex);
|
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throw DecompileFail("Unhandled instruction");
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case OpCode::Id::TEXS: {
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ASSERT_MSG(instr.attribute.fmt20.size == 4, "untested");
|
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const std::string op_a = GetRegister(instr.gpr8);
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const std::string op_b = GetRegister(instr.gpr20);
|
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const std::string sampler = GetSampler(instr.sampler);
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const std::string coord = "vec2(" + op_a + ", " + op_b + ")";
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const std::string texture = "texture(" + sampler + ", " + coord + ")";
|
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for (unsigned elem = 0; elem < instr.attribute.fmt20.size; ++elem) {
|
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SetDest(elem, GetRegister(instr.gpr0, elem), texture, 1, 4);
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}
|
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break;
|
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}
|
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default: {
|
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NGLOG_CRITICAL(HW_GPU, "Unhandled memory instruction: {} ({}): {}",
|
||||
static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
|
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OpCode::GetInfo(instr.opcode).name, instr.hex);
|
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UNREACHABLE();
|
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}
|
||||
}
|
||||
break;
|
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}
|
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@ -342,14 +423,18 @@ private:
|
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offset = PROGRAM_END - 1;
|
||||
break;
|
||||
}
|
||||
|
||||
default: {
|
||||
LOG_CRITICAL(HW_GPU, "Unhandled instruction: 0x%02x (%s): 0x%08x",
|
||||
static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
|
||||
OpCode::GetInfo(instr.opcode).name.c_str(), instr.hex);
|
||||
throw DecompileFail("Unhandled instruction");
|
||||
case OpCode::Id::IPA: {
|
||||
const auto& attribute = instr.attribute.fmt28;
|
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std::string dest = GetRegister(instr.gpr0);
|
||||
SetDest(attribute.element, dest, GetInputAttribute(attribute.index), 1, 4);
|
||||
break;
|
||||
}
|
||||
default: {
|
||||
NGLOG_CRITICAL(HW_GPU, "Unhandled instruction: {} ({}): {}",
|
||||
static_cast<unsigned>(instr.opcode.EffectiveOpCode()),
|
||||
OpCode::GetInfo(instr.opcode).name, instr.hex);
|
||||
UNREACHABLE();
|
||||
}
|
||||
}
|
||||
|
||||
break;
|
||||
@ -514,7 +599,7 @@ boost::optional<ProgramResult> DecompileProgram(const ProgramCode& program_code,
|
||||
GLSLGenerator generator(subroutines, program_code, main_offset, stage);
|
||||
return ProgramResult{generator.GetShaderCode(), generator.GetEntries()};
|
||||
} catch (const DecompileFail& exception) {
|
||||
LOG_ERROR(HW_GPU, "Shader decompilation failed: %s", exception.what());
|
||||
NGLOG_ERROR(HW_GPU, "Shader decompilation failed: {}", exception.what());
|
||||
}
|
||||
return boost::none;
|
||||
}
|
||||
|
@ -27,10 +27,13 @@ out gl_PerVertex {
|
||||
vec4 gl_Position;
|
||||
};
|
||||
|
||||
out vec4 position;
|
||||
|
||||
void main() {
|
||||
exec_shader();
|
||||
}
|
||||
|
||||
gl_Position = position;
|
||||
}
|
||||
)";
|
||||
out += program.first;
|
||||
return {out, program.second};
|
||||
@ -46,6 +49,7 @@ ProgramResult GenerateFragmentShader(const ShaderSetup& setup, const MaxwellFSCo
|
||||
.get_value_or({});
|
||||
out += R"(
|
||||
|
||||
in vec4 position;
|
||||
out vec4 color;
|
||||
|
||||
uniform sampler2D tex[32];
|
||||
|
Loading…
Reference in New Issue
Block a user