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https://github.com/yuzu-emu/yuzu.git
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Merge pull request #3784 from ReinUsesLisp/shader-memory-util
shader/memory_util: Deduplicate code
This commit is contained in:
commit
72b73d22ab
@ -124,6 +124,8 @@ add_library(video_core STATIC
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shader/decode.cpp
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shader/expr.cpp
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shader/expr.h
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shader/memory_util.cpp
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shader/memory_util.h
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shader/node_helper.cpp
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shader/node_helper.h
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shader/node.h
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@ -10,8 +10,6 @@
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#include <thread>
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#include <unordered_set>
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#include <boost/functional/hash.hpp>
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#include "common/alignment.h"
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#include "common/assert.h"
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#include "common/logging/log.h"
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@ -28,76 +26,26 @@
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#include "video_core/renderer_opengl/gl_shader_disk_cache.h"
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#include "video_core/renderer_opengl/gl_state_tracker.h"
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#include "video_core/renderer_opengl/utils.h"
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#include "video_core/shader/memory_util.h"
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#include "video_core/shader/registry.h"
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#include "video_core/shader/shader_ir.h"
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namespace OpenGL {
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using Tegra::Engines::ShaderType;
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using VideoCommon::Shader::GetShaderAddress;
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using VideoCommon::Shader::GetShaderCode;
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using VideoCommon::Shader::GetUniqueIdentifier;
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using VideoCommon::Shader::KERNEL_MAIN_OFFSET;
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using VideoCommon::Shader::ProgramCode;
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using VideoCommon::Shader::Registry;
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using VideoCommon::Shader::ShaderIR;
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using VideoCommon::Shader::STAGE_MAIN_OFFSET;
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namespace {
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constexpr u32 STAGE_MAIN_OFFSET = 10;
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constexpr u32 KERNEL_MAIN_OFFSET = 0;
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constexpr VideoCommon::Shader::CompilerSettings COMPILER_SETTINGS{};
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/// Gets the address for the specified shader stage program
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GPUVAddr GetShaderAddress(Core::System& system, Maxwell::ShaderProgram program) {
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const auto& gpu{system.GPU().Maxwell3D()};
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const auto& shader_config{gpu.regs.shader_config[static_cast<std::size_t>(program)]};
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return gpu.regs.code_address.CodeAddress() + shader_config.offset;
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}
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/// Gets if the current instruction offset is a scheduler instruction
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constexpr bool IsSchedInstruction(std::size_t offset, std::size_t main_offset) {
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// Sched instructions appear once every 4 instructions.
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constexpr std::size_t SchedPeriod = 4;
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const std::size_t absolute_offset = offset - main_offset;
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return (absolute_offset % SchedPeriod) == 0;
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}
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/// Calculates the size of a program stream
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std::size_t CalculateProgramSize(const ProgramCode& program) {
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constexpr std::size_t start_offset = 10;
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// This is the encoded version of BRA that jumps to itself. All Nvidia
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// shaders end with one.
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constexpr u64 self_jumping_branch = 0xE2400FFFFF07000FULL;
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constexpr u64 mask = 0xFFFFFFFFFF7FFFFFULL;
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std::size_t offset = start_offset;
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while (offset < program.size()) {
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const u64 instruction = program[offset];
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if (!IsSchedInstruction(offset, start_offset)) {
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if ((instruction & mask) == self_jumping_branch) {
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// End on Maxwell's "nop" instruction
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break;
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}
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if (instruction == 0) {
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break;
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}
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}
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offset++;
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}
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// The last instruction is included in the program size
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return std::min(offset + 1, program.size());
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}
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/// Gets the shader program code from memory for the specified address
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ProgramCode GetShaderCode(Tegra::MemoryManager& memory_manager, const GPUVAddr gpu_addr,
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const u8* host_ptr) {
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ProgramCode code(VideoCommon::Shader::MAX_PROGRAM_LENGTH);
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ASSERT_OR_EXECUTE(host_ptr != nullptr, {
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std::fill(code.begin(), code.end(), 0);
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return code;
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});
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memory_manager.ReadBlockUnsafe(gpu_addr, code.data(), code.size() * sizeof(u64));
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code.resize(CalculateProgramSize(code));
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return code;
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}
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/// Gets the shader type from a Maxwell program type
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constexpr GLenum GetGLShaderType(ShaderType shader_type) {
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switch (shader_type) {
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@ -114,17 +62,6 @@ constexpr GLenum GetGLShaderType(ShaderType shader_type) {
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}
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}
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/// Hashes one (or two) program streams
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u64 GetUniqueIdentifier(ShaderType shader_type, bool is_a, const ProgramCode& code,
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const ProgramCode& code_b = {}) {
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u64 unique_identifier = boost::hash_value(code);
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if (is_a) {
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// VertexA programs include two programs
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boost::hash_combine(unique_identifier, boost::hash_value(code_b));
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}
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return unique_identifier;
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}
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constexpr const char* GetShaderTypeName(ShaderType shader_type) {
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switch (shader_type) {
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case ShaderType::Vertex:
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@ -456,11 +393,12 @@ Shader ShaderCacheOpenGL::GetStageProgram(Maxwell::ShaderProgram program) {
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const auto host_ptr{memory_manager.GetPointer(address)};
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// No shader found - create a new one
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ProgramCode code{GetShaderCode(memory_manager, address, host_ptr)};
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ProgramCode code{GetShaderCode(memory_manager, address, host_ptr, false)};
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ProgramCode code_b;
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if (program == Maxwell::ShaderProgram::VertexA) {
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const GPUVAddr address_b{GetShaderAddress(system, Maxwell::ShaderProgram::VertexB)};
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code_b = GetShaderCode(memory_manager, address_b, memory_manager.GetPointer(address_b));
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const u8* host_ptr_b = memory_manager.GetPointer(address_b);
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code_b = GetShaderCode(memory_manager, address_b, host_ptr_b, false);
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}
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const auto unique_identifier = GetUniqueIdentifier(
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@ -498,7 +436,7 @@ Shader ShaderCacheOpenGL::GetComputeKernel(GPUVAddr code_addr) {
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const auto host_ptr{memory_manager.GetPointer(code_addr)};
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// No kernel found, create a new one
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auto code{GetShaderCode(memory_manager, code_addr, host_ptr)};
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auto code{GetShaderCode(memory_manager, code_addr, host_ptr, true)};
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const auto unique_identifier{GetUniqueIdentifier(ShaderType::Compute, false, code)};
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const ShaderParameters params{system, disk_cache, device,
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@ -27,12 +27,18 @@
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#include "video_core/renderer_vulkan/vk_update_descriptor.h"
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#include "video_core/renderer_vulkan/wrapper.h"
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#include "video_core/shader/compiler_settings.h"
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#include "video_core/shader/memory_util.h"
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namespace Vulkan {
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MICROPROFILE_DECLARE(Vulkan_PipelineCache);
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using Tegra::Engines::ShaderType;
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using VideoCommon::Shader::GetShaderAddress;
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using VideoCommon::Shader::GetShaderCode;
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using VideoCommon::Shader::KERNEL_MAIN_OFFSET;
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using VideoCommon::Shader::ProgramCode;
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using VideoCommon::Shader::STAGE_MAIN_OFFSET;
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namespace {
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@ -45,60 +51,6 @@ constexpr VkDescriptorType STORAGE_IMAGE = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE;
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constexpr VideoCommon::Shader::CompilerSettings compiler_settings{
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VideoCommon::Shader::CompileDepth::FullDecompile};
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/// Gets the address for the specified shader stage program
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GPUVAddr GetShaderAddress(Core::System& system, Maxwell::ShaderProgram program) {
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const auto& gpu{system.GPU().Maxwell3D()};
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const auto& shader_config{gpu.regs.shader_config[static_cast<std::size_t>(program)]};
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return gpu.regs.code_address.CodeAddress() + shader_config.offset;
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}
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/// Gets if the current instruction offset is a scheduler instruction
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constexpr bool IsSchedInstruction(std::size_t offset, std::size_t main_offset) {
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// Sched instructions appear once every 4 instructions.
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constexpr std::size_t SchedPeriod = 4;
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const std::size_t absolute_offset = offset - main_offset;
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return (absolute_offset % SchedPeriod) == 0;
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}
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/// Calculates the size of a program stream
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std::size_t CalculateProgramSize(const ProgramCode& program, bool is_compute) {
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const std::size_t start_offset = is_compute ? 0 : 10;
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// This is the encoded version of BRA that jumps to itself. All Nvidia
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// shaders end with one.
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constexpr u64 self_jumping_branch = 0xE2400FFFFF07000FULL;
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constexpr u64 mask = 0xFFFFFFFFFF7FFFFFULL;
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std::size_t offset = start_offset;
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while (offset < program.size()) {
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const u64 instruction = program[offset];
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if (!IsSchedInstruction(offset, start_offset)) {
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if ((instruction & mask) == self_jumping_branch) {
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// End on Maxwell's "nop" instruction
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break;
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}
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if (instruction == 0) {
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break;
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}
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}
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++offset;
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}
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// The last instruction is included in the program size
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return std::min(offset + 1, program.size());
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}
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/// Gets the shader program code from memory for the specified address
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ProgramCode GetShaderCode(Tegra::MemoryManager& memory_manager, const GPUVAddr gpu_addr,
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const u8* host_ptr, bool is_compute) {
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ProgramCode program_code(VideoCommon::Shader::MAX_PROGRAM_LENGTH);
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ASSERT_OR_EXECUTE(host_ptr != nullptr, {
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std::fill(program_code.begin(), program_code.end(), 0);
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return program_code;
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});
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memory_manager.ReadBlockUnsafe(gpu_addr, program_code.data(),
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program_code.size() * sizeof(u64));
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program_code.resize(CalculateProgramSize(program_code, is_compute));
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return program_code;
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}
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constexpr std::size_t GetStageFromProgram(std::size_t program) {
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return program == 0 ? 0 : program - 1;
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}
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@ -230,9 +182,9 @@ std::array<Shader, Maxwell::MaxShaderProgram> VKPipelineCache::GetShaders() {
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const auto host_ptr{memory_manager.GetPointer(program_addr)};
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// No shader found - create a new one
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constexpr u32 stage_offset = 10;
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constexpr u32 stage_offset = STAGE_MAIN_OFFSET;
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const auto stage = static_cast<Tegra::Engines::ShaderType>(index == 0 ? 0 : index - 1);
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auto code = GetShaderCode(memory_manager, program_addr, host_ptr, false);
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ProgramCode code = GetShaderCode(memory_manager, program_addr, host_ptr, false);
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shader = std::make_shared<CachedShader>(system, stage, program_addr, *cpu_addr,
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std::move(code), stage_offset);
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@ -288,11 +240,10 @@ VKComputePipeline& VKPipelineCache::GetComputePipeline(const ComputePipelineCach
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// No shader found - create a new one
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const auto host_ptr = memory_manager.GetPointer(program_addr);
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auto code = GetShaderCode(memory_manager, program_addr, host_ptr, true);
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constexpr u32 kernel_main_offset = 0;
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ProgramCode code = GetShaderCode(memory_manager, program_addr, host_ptr, true);
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shader = std::make_shared<CachedShader>(system, Tegra::Engines::ShaderType::Compute,
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program_addr, *cpu_addr, std::move(code),
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kernel_main_offset);
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KERNEL_MAIN_OFFSET);
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if (cpu_addr) {
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Register(shader);
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} else {
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@ -24,6 +24,7 @@
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#include "video_core/renderer_vulkan/vk_resource_manager.h"
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#include "video_core/renderer_vulkan/vk_shader_decompiler.h"
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#include "video_core/renderer_vulkan/wrapper.h"
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#include "video_core/shader/memory_util.h"
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#include "video_core/shader/registry.h"
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#include "video_core/shader/shader_ir.h"
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#include "video_core/surface.h"
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@ -46,8 +47,6 @@ class CachedShader;
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using Shader = std::shared_ptr<CachedShader>;
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using Maxwell = Tegra::Engines::Maxwell3D::Regs;
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using ProgramCode = std::vector<u64>;
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struct GraphicsPipelineCacheKey {
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FixedPipelineState fixed_state;
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RenderPassParams renderpass_params;
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@ -108,7 +107,8 @@ namespace Vulkan {
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class CachedShader final : public RasterizerCacheObject {
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public:
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explicit CachedShader(Core::System& system, Tegra::Engines::ShaderType stage, GPUVAddr gpu_addr,
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VAddr cpu_addr, ProgramCode program_code, u32 main_offset);
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VAddr cpu_addr, VideoCommon::Shader::ProgramCode program_code,
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u32 main_offset);
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~CachedShader();
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GPUVAddr GetGpuAddr() const {
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@ -140,7 +140,7 @@ private:
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Tegra::Engines::ShaderType stage);
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GPUVAddr gpu_addr{};
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ProgramCode program_code;
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VideoCommon::Shader::ProgramCode program_code;
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VideoCommon::Shader::Registry registry;
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VideoCommon::Shader::ShaderIR shader_ir;
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ShaderEntries entries;
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@ -13,6 +13,7 @@
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#include "common/common_types.h"
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#include "video_core/shader/ast.h"
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#include "video_core/shader/control_flow.h"
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#include "video_core/shader/memory_util.h"
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#include "video_core/shader/registry.h"
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#include "video_core/shader/shader_ir.h"
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@ -115,17 +116,6 @@ Pred GetPredicate(u32 index, bool negated) {
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return static_cast<Pred>(static_cast<u64>(index) + (negated ? 8ULL : 0ULL));
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}
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/**
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* Returns whether the instruction at the specified offset is a 'sched' instruction.
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* Sched instructions always appear before a sequence of 3 instructions.
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*/
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constexpr bool IsSchedInstruction(u32 offset, u32 main_offset) {
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constexpr u32 SchedPeriod = 4;
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u32 absolute_offset = offset - main_offset;
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return (absolute_offset % SchedPeriod) == 0;
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}
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enum class ParseResult : u32 {
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ControlCaught,
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BlockEnd,
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@ -13,6 +13,7 @@
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/engines/shader_header.h"
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#include "video_core/shader/control_flow.h"
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#include "video_core/shader/memory_util.h"
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#include "video_core/shader/node_helper.h"
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#include "video_core/shader/shader_ir.h"
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@ -23,17 +24,6 @@ using Tegra::Shader::OpCode;
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namespace {
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/**
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* Returns whether the instruction at the specified offset is a 'sched' instruction.
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* Sched instructions always appear before a sequence of 3 instructions.
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*/
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constexpr bool IsSchedInstruction(u32 offset, u32 main_offset) {
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constexpr u32 SchedPeriod = 4;
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u32 absolute_offset = offset - main_offset;
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return (absolute_offset % SchedPeriod) == 0;
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}
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void DeduceTextureHandlerSize(VideoCore::GuestDriverProfile& gpu_driver,
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const std::list<Sampler>& used_samplers) {
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if (gpu_driver.IsTextureHandlerSizeKnown() || used_samplers.size() <= 1) {
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77
src/video_core/shader/memory_util.cpp
Normal file
77
src/video_core/shader/memory_util.cpp
Normal file
@ -0,0 +1,77 @@
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// Copyright 2020 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <cstddef>
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#include <boost/container_hash/hash.hpp>
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#include "common/common_types.h"
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#include "core/core.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/memory_manager.h"
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#include "video_core/shader/memory_util.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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GPUVAddr GetShaderAddress(Core::System& system,
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Tegra::Engines::Maxwell3D::Regs::ShaderProgram program) {
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const auto& gpu{system.GPU().Maxwell3D()};
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const auto& shader_config{gpu.regs.shader_config[static_cast<std::size_t>(program)]};
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return gpu.regs.code_address.CodeAddress() + shader_config.offset;
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}
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bool IsSchedInstruction(std::size_t offset, std::size_t main_offset) {
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// Sched instructions appear once every 4 instructions.
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constexpr std::size_t SchedPeriod = 4;
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const std::size_t absolute_offset = offset - main_offset;
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return (absolute_offset % SchedPeriod) == 0;
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}
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std::size_t CalculateProgramSize(const ProgramCode& program, bool is_compute) {
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// This is the encoded version of BRA that jumps to itself. All Nvidia
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// shaders end with one.
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static constexpr u64 SELF_JUMPING_BRANCH = 0xE2400FFFFF07000FULL;
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static constexpr u64 MASK = 0xFFFFFFFFFF7FFFFFULL;
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const std::size_t start_offset = is_compute ? KERNEL_MAIN_OFFSET : STAGE_MAIN_OFFSET;
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std::size_t offset = start_offset;
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while (offset < program.size()) {
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const u64 instruction = program[offset];
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if (!IsSchedInstruction(offset, start_offset)) {
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if ((instruction & MASK) == SELF_JUMPING_BRANCH) {
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// End on Maxwell's "nop" instruction
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break;
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}
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if (instruction == 0) {
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break;
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}
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}
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++offset;
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}
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// The last instruction is included in the program size
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return std::min(offset + 1, program.size());
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}
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ProgramCode GetShaderCode(Tegra::MemoryManager& memory_manager, GPUVAddr gpu_addr,
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const u8* host_ptr, bool is_compute) {
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ProgramCode code(VideoCommon::Shader::MAX_PROGRAM_LENGTH);
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ASSERT_OR_EXECUTE(host_ptr != nullptr, { return code; });
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memory_manager.ReadBlockUnsafe(gpu_addr, code.data(), code.size() * sizeof(u64));
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code.resize(CalculateProgramSize(code, is_compute));
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return code;
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}
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u64 GetUniqueIdentifier(Tegra::Engines::ShaderType shader_type, bool is_a, const ProgramCode& code,
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const ProgramCode& code_b) {
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u64 unique_identifier = boost::hash_value(code);
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if (is_a) {
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// VertexA programs include two programs
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boost::hash_combine(unique_identifier, boost::hash_value(code_b));
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}
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return unique_identifier;
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}
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} // namespace VideoCommon::Shader
|
47
src/video_core/shader/memory_util.h
Normal file
47
src/video_core/shader/memory_util.h
Normal file
@ -0,0 +1,47 @@
|
||||
// Copyright 2020 yuzu Emulator Project
|
||||
// Licensed under GPLv2 or any later version
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <cstddef>
|
||||
#include <vector>
|
||||
|
||||
#include "common/common_types.h"
|
||||
#include "video_core/engines/maxwell_3d.h"
|
||||
#include "video_core/engines/shader_type.h"
|
||||
|
||||
namespace Core {
|
||||
class System;
|
||||
}
|
||||
|
||||
namespace Tegra {
|
||||
class MemoryManager;
|
||||
}
|
||||
|
||||
namespace VideoCommon::Shader {
|
||||
|
||||
using ProgramCode = std::vector<u64>;
|
||||
|
||||
constexpr u32 STAGE_MAIN_OFFSET = 10;
|
||||
constexpr u32 KERNEL_MAIN_OFFSET = 0;
|
||||
|
||||
/// Gets the address for the specified shader stage program
|
||||
GPUVAddr GetShaderAddress(Core::System& system,
|
||||
Tegra::Engines::Maxwell3D::Regs::ShaderProgram program);
|
||||
|
||||
/// Gets if the current instruction offset is a scheduler instruction
|
||||
bool IsSchedInstruction(std::size_t offset, std::size_t main_offset);
|
||||
|
||||
/// Calculates the size of a program stream
|
||||
std::size_t CalculateProgramSize(const ProgramCode& program, bool is_compute);
|
||||
|
||||
/// Gets the shader program code from memory for the specified address
|
||||
ProgramCode GetShaderCode(Tegra::MemoryManager& memory_manager, GPUVAddr gpu_addr,
|
||||
const u8* host_ptr, bool is_compute);
|
||||
|
||||
/// Hashes one (or two) program streams
|
||||
u64 GetUniqueIdentifier(Tegra::Engines::ShaderType shader_type, bool is_a, const ProgramCode& code,
|
||||
const ProgramCode& code_b = {});
|
||||
|
||||
} // namespace VideoCommon::Shader
|
@ -18,6 +18,7 @@
|
||||
#include "video_core/engines/shader_header.h"
|
||||
#include "video_core/shader/ast.h"
|
||||
#include "video_core/shader/compiler_settings.h"
|
||||
#include "video_core/shader/memory_util.h"
|
||||
#include "video_core/shader/node.h"
|
||||
#include "video_core/shader/registry.h"
|
||||
|
||||
@ -25,8 +26,6 @@ namespace VideoCommon::Shader {
|
||||
|
||||
struct ShaderBlock;
|
||||
|
||||
using ProgramCode = std::vector<u64>;
|
||||
|
||||
constexpr u32 MAX_PROGRAM_LENGTH = 0x1000;
|
||||
|
||||
class ConstBuffer {
|
||||
|
Loading…
Reference in New Issue
Block a user