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https://github.com/yuzu-emu/yuzu.git
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Merge pull request #6597 from FernandoS27/accelerate-dma
DMAEngine: Introduce Accelerate DMA.
This commit is contained in:
commit
776f391ff6
@ -164,6 +164,8 @@ public:
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/// Pop asynchronous downloads
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void PopAsyncFlushes();
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[[nodiscard]] bool DMACopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount);
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/// Return true when a CPU region is modified from the GPU
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[[nodiscard]] bool IsRegionGpuModified(VAddr addr, size_t size);
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@ -200,6 +202,36 @@ private:
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}
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}
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template <typename Func>
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void ForEachWrittenRange(VAddr cpu_addr, u64 size, Func&& func) {
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const VAddr start_address = cpu_addr;
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const VAddr end_address = start_address + size;
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const VAddr search_base =
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static_cast<VAddr>(std::min<s64>(0LL, static_cast<s64>(start_address - size)));
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const IntervalType search_interval{search_base, search_base + 1};
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auto it = common_ranges.lower_bound(search_interval);
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if (it == common_ranges.end()) {
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it = common_ranges.begin();
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}
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for (; it != common_ranges.end(); it++) {
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VAddr inter_addr_end = it->upper();
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VAddr inter_addr = it->lower();
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if (inter_addr >= end_address) {
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break;
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}
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if (inter_addr_end <= start_address) {
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continue;
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}
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if (inter_addr_end > end_address) {
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inter_addr_end = end_address;
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}
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if (inter_addr < start_address) {
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inter_addr = start_address;
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}
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func(inter_addr, inter_addr_end);
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}
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}
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static bool IsRangeGranular(VAddr cpu_addr, size_t size) {
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return (cpu_addr & ~Core::Memory::PAGE_MASK) ==
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((cpu_addr + size) & ~Core::Memory::PAGE_MASK);
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@ -430,6 +462,68 @@ void BufferCache<P>::DownloadMemory(VAddr cpu_addr, u64 size) {
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});
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}
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template <class P>
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bool BufferCache<P>::DMACopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) {
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const std::optional<VAddr> cpu_src_address = gpu_memory.GpuToCpuAddress(src_address);
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const std::optional<VAddr> cpu_dest_address = gpu_memory.GpuToCpuAddress(dest_address);
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if (!cpu_src_address || !cpu_dest_address) {
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return false;
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}
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const bool source_dirty = IsRegionGpuModified(*cpu_src_address, amount);
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const bool dest_dirty = IsRegionGpuModified(*cpu_dest_address, amount);
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if (!source_dirty && !dest_dirty) {
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return false;
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}
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const IntervalType subtract_interval{*cpu_dest_address, *cpu_dest_address + amount};
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uncommitted_ranges.subtract(subtract_interval);
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for (auto& interval_set : committed_ranges) {
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interval_set.subtract(subtract_interval);
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}
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BufferId buffer_a;
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BufferId buffer_b;
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do {
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has_deleted_buffers = false;
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buffer_a = FindBuffer(*cpu_src_address, static_cast<u32>(amount));
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buffer_b = FindBuffer(*cpu_dest_address, static_cast<u32>(amount));
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} while (has_deleted_buffers);
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auto& src_buffer = slot_buffers[buffer_a];
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auto& dest_buffer = slot_buffers[buffer_b];
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SynchronizeBuffer(src_buffer, *cpu_src_address, static_cast<u32>(amount));
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SynchronizeBuffer(dest_buffer, *cpu_dest_address, static_cast<u32>(amount));
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std::array copies{BufferCopy{
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.src_offset = src_buffer.Offset(*cpu_src_address),
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.dst_offset = dest_buffer.Offset(*cpu_dest_address),
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.size = amount,
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}};
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boost::container::small_vector<IntervalType, 4> tmp_intervals;
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auto mirror = [&](VAddr base_address, VAddr base_address_end) {
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const u64 size = base_address_end - base_address;
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const VAddr diff = base_address - *cpu_src_address;
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const VAddr new_base_address = *cpu_dest_address + diff;
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const IntervalType add_interval{new_base_address, new_base_address + size};
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uncommitted_ranges.add(add_interval);
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tmp_intervals.push_back(add_interval);
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};
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ForEachWrittenRange(*cpu_src_address, amount, mirror);
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// This subtraction in this order is important for overlapping copies.
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common_ranges.subtract(subtract_interval);
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for (const IntervalType add_interval : tmp_intervals) {
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common_ranges.add(add_interval);
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}
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runtime.CopyBuffer(dest_buffer, src_buffer, copies);
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if (source_dirty) {
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dest_buffer.MarkRegionAsGpuModified(*cpu_dest_address, amount);
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}
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std::vector<u8> tmp_buffer(amount);
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cpu_memory.ReadBlockUnsafe(*cpu_src_address, tmp_buffer.data(), amount);
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cpu_memory.WriteBlockUnsafe(*cpu_dest_address, tmp_buffer.data(), amount);
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return true;
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}
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template <class P>
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void BufferCache<P>::BindGraphicsUniformBuffer(size_t stage, u32 index, GPUVAddr gpu_addr,
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u32 size) {
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@ -616,30 +710,7 @@ void BufferCache<P>::CommitAsyncFlushesHigh() {
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const VAddr start_address = buffer_addr + range_offset;
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const VAddr end_address = start_address + range_size;
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const IntervalType search_interval{cpu_addr, 1};
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auto it = common_ranges.lower_bound(search_interval);
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if (it == common_ranges.end()) {
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it = common_ranges.begin();
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}
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while (it != common_ranges.end()) {
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VAddr inter_addr_end = it->upper();
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VAddr inter_addr = it->lower();
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if (inter_addr >= end_address) {
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break;
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}
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if (inter_addr_end <= start_address) {
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it++;
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continue;
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}
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if (inter_addr_end > end_address) {
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inter_addr_end = end_address;
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}
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if (inter_addr < start_address) {
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inter_addr = start_address;
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}
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add_download(inter_addr, inter_addr_end);
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it++;
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}
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ForEachWrittenRange(start_address, range_size, add_download);
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const IntervalType subtract_interval{start_address, end_address};
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common_ranges.subtract(subtract_interval);
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});
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@ -737,7 +808,9 @@ void BufferCache<P>::BindHostIndexBuffer() {
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const u32 size = index_buffer.size;
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SynchronizeBuffer(buffer, index_buffer.cpu_addr, size);
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if constexpr (HAS_FULL_INDEX_AND_PRIMITIVE_SUPPORT) {
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runtime.BindIndexBuffer(buffer, offset, size);
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const u32 new_offset = offset + maxwell3d.regs.index_array.first *
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maxwell3d.regs.index_array.FormatSizeInBytes();
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runtime.BindIndexBuffer(buffer, new_offset, size);
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} else {
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runtime.BindIndexBuffer(maxwell3d.regs.draw.topology, maxwell3d.regs.index_array.format,
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maxwell3d.regs.index_array.first, maxwell3d.regs.index_array.count,
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@ -951,7 +1024,7 @@ void BufferCache<P>::UpdateIndexBuffer() {
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const GPUVAddr gpu_addr_end = index_array.EndAddress();
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const std::optional<VAddr> cpu_addr = gpu_memory.GpuToCpuAddress(gpu_addr_begin);
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const u32 address_size = static_cast<u32>(gpu_addr_end - gpu_addr_begin);
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const u32 draw_size = index_array.count * index_array.FormatSizeInBytes();
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const u32 draw_size = (index_array.count + index_array.first) * index_array.FormatSizeInBytes();
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const u32 size = std::min(address_size, draw_size);
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if (size == 0 || !cpu_addr) {
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index_buffer = NULL_BINDING;
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@ -1350,30 +1423,7 @@ void BufferCache<P>::DownloadBufferMemory(Buffer& buffer, VAddr cpu_addr, u64 si
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const VAddr start_address = buffer_addr + range_offset;
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const VAddr end_address = start_address + range_size;
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const IntervalType search_interval{start_address - range_size, 1};
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auto it = common_ranges.lower_bound(search_interval);
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if (it == common_ranges.end()) {
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it = common_ranges.begin();
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}
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while (it != common_ranges.end()) {
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VAddr inter_addr_end = it->upper();
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VAddr inter_addr = it->lower();
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if (inter_addr >= end_address) {
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break;
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}
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if (inter_addr_end <= start_address) {
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it++;
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continue;
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}
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if (inter_addr_end > end_address) {
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inter_addr_end = end_address;
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}
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if (inter_addr < start_address) {
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inter_addr = start_address;
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}
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add_download(inter_addr, inter_addr_end);
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it++;
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}
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ForEachWrittenRange(start_address, range_size, add_download);
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const IntervalType subtract_interval{start_address, end_address};
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common_ranges.subtract(subtract_interval);
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});
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@ -21,6 +21,10 @@ MaxwellDMA::MaxwellDMA(Core::System& system_, MemoryManager& memory_manager_)
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MaxwellDMA::~MaxwellDMA() = default;
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void MaxwellDMA::BindRasterizer(VideoCore::RasterizerInterface* rasterizer_) {
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rasterizer = rasterizer_;
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}
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void MaxwellDMA::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
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ASSERT_MSG(method < NUM_REGS, "Invalid MaxwellDMA register");
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@ -44,7 +48,6 @@ void MaxwellDMA::Launch() {
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// TODO(Subv): Perform more research and implement all features of this engine.
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const LaunchDMA& launch = regs.launch_dma;
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ASSERT(launch.remap_enable == 0);
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ASSERT(launch.semaphore_type == LaunchDMA::SemaphoreType::NONE);
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ASSERT(launch.interrupt_type == LaunchDMA::InterruptType::NONE);
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ASSERT(launch.data_transfer_type == LaunchDMA::DataTransferType::NON_PIPELINED);
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@ -77,11 +80,29 @@ void MaxwellDMA::CopyPitchToPitch() {
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// When `multi_line_enable` bit is disabled the copy is performed as if we were copying a 1D
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// buffer of length `line_length_in`.
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// Otherwise we copy a 2D image of dimensions (line_length_in, line_count).
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auto& accelerate = rasterizer->AccessAccelerateDMA();
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if (!regs.launch_dma.multi_line_enable) {
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memory_manager.CopyBlock(regs.offset_out, regs.offset_in, regs.line_length_in);
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const bool is_buffer_clear = regs.launch_dma.remap_enable != 0 &&
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regs.remap_const.dst_x == RemapConst::Swizzle::CONST_A;
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// TODO: allow multisized components.
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if (is_buffer_clear) {
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ASSERT(regs.remap_const.component_size_minus_one == 3);
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std::vector<u32> tmp_buffer(regs.line_length_in, regs.remap_consta_value);
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memory_manager.WriteBlock(regs.offset_out, reinterpret_cast<u8*>(tmp_buffer.data()),
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regs.line_length_in * sizeof(u32));
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return;
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}
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UNIMPLEMENTED_IF(regs.launch_dma.remap_enable != 0);
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if (!accelerate.BufferCopy(regs.offset_in, regs.offset_out, regs.line_length_in)) {
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std::vector<u8> tmp_buffer(regs.line_length_in);
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memory_manager.ReadBlockUnsafe(regs.offset_in, tmp_buffer.data(), regs.line_length_in);
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memory_manager.WriteBlock(regs.offset_out, tmp_buffer.data(), regs.line_length_in);
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}
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return;
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}
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UNIMPLEMENTED_IF(regs.launch_dma.remap_enable != 0);
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// Perform a line-by-line copy.
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// We're going to take a subrect of size (line_length_in, line_count) from the source rectangle.
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// There is no need to manually flush/invalidate the regions because CopyBlock does that for us.
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@ -105,6 +126,7 @@ void MaxwellDMA::CopyBlockLinearToPitch() {
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}
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// Deswizzle the input and copy it over.
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UNIMPLEMENTED_IF(regs.launch_dma.remap_enable != 0);
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const u32 bytes_per_pixel = regs.pitch_out / regs.line_length_in;
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const Parameters& src_params = regs.src_params;
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const u32 width = src_params.width;
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@ -134,6 +156,7 @@ void MaxwellDMA::CopyBlockLinearToPitch() {
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void MaxwellDMA::CopyPitchToBlockLinear() {
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UNIMPLEMENTED_IF_MSG(regs.dst_params.block_size.width != 0, "Block width is not one");
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UNIMPLEMENTED_IF(regs.launch_dma.remap_enable != 0);
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const auto& dst_params = regs.dst_params;
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const u32 bytes_per_pixel = regs.pitch_in / regs.line_length_in;
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@ -156,13 +179,8 @@ void MaxwellDMA::CopyPitchToBlockLinear() {
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write_buffer.resize(dst_size);
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}
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if (Settings::IsGPULevelExtreme()) {
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memory_manager.ReadBlock(regs.offset_in, read_buffer.data(), src_size);
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memory_manager.ReadBlock(regs.offset_out, write_buffer.data(), dst_size);
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} else {
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memory_manager.ReadBlockUnsafe(regs.offset_in, read_buffer.data(), src_size);
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memory_manager.ReadBlockUnsafe(regs.offset_out, write_buffer.data(), dst_size);
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}
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memory_manager.ReadBlock(regs.offset_in, read_buffer.data(), src_size);
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memory_manager.ReadBlock(regs.offset_out, write_buffer.data(), dst_size);
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// If the input is linear and the output is tiled, swizzle the input and copy it over.
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if (regs.dst_params.block_size.depth > 0) {
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@ -21,8 +21,18 @@ namespace Tegra {
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class MemoryManager;
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}
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namespace VideoCore {
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class RasterizerInterface;
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}
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namespace Tegra::Engines {
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class AccelerateDMAInterface {
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public:
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/// Write the value to the register identified by method.
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virtual bool BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) = 0;
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};
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/**
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* This engine is known as gk104_copy. Documentation can be found in:
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* https://github.com/NVIDIA/open-gpu-doc/blob/master/classes/dma-copy/clb0b5.h
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@ -187,6 +197,8 @@ public:
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};
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static_assert(sizeof(RemapConst) == 12);
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void BindRasterizer(VideoCore::RasterizerInterface* rasterizer);
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explicit MaxwellDMA(Core::System& system_, MemoryManager& memory_manager_);
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~MaxwellDMA() override;
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@ -213,6 +225,7 @@ private:
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Core::System& system;
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MemoryManager& memory_manager;
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VideoCore::RasterizerInterface* rasterizer;
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std::vector<u8> read_buffer;
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std::vector<u8> write_buffer;
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@ -240,7 +253,9 @@ private:
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u32 pitch_out;
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u32 line_length_in;
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u32 line_count;
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u32 reserved06[0xb8];
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u32 reserved06[0xb6];
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u32 remap_consta_value;
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u32 remap_constb_value;
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RemapConst remap_const;
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Parameters dst_params;
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u32 reserved07[0x1];
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@ -50,6 +50,7 @@ void GPU::BindRenderer(std::unique_ptr<VideoCore::RendererBase> renderer_) {
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maxwell_3d->BindRasterizer(rasterizer);
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fermi_2d->BindRasterizer(rasterizer);
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kepler_compute->BindRasterizer(rasterizer);
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maxwell_dma->BindRasterizer(rasterizer);
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}
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Engines::Maxwell3D& GPU::Maxwell3D() {
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@ -15,7 +15,10 @@
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namespace Tegra {
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class MemoryManager;
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namespace Engines {
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class AccelerateDMAInterface;
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}
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} // namespace Tegra
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namespace VideoCore {
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@ -119,6 +122,8 @@ public:
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return false;
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}
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[[nodiscard]] virtual Tegra::Engines::AccelerateDMAInterface& AccessAccelerateDMA() = 0;
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/// Attempt to use a faster method to display the framebuffer to screen
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[[nodiscard]] virtual bool AccelerateDisplay(const Tegra::FramebufferConfig& config,
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VAddr framebuffer_addr, u32 pixel_stride) {
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|
@ -171,7 +171,7 @@ RasterizerOpenGL::RasterizerOpenGL(Core::Frontend::EmuWindow& emu_window_, Tegra
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buffer_cache_runtime(device),
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buffer_cache(*this, maxwell3d, kepler_compute, gpu_memory, cpu_memory_, buffer_cache_runtime),
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shader_cache(*this, emu_window_, gpu, maxwell3d, kepler_compute, gpu_memory, device),
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query_cache(*this, maxwell3d, gpu_memory),
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query_cache(*this, maxwell3d, gpu_memory), accelerate_dma(buffer_cache),
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fence_manager(*this, gpu, texture_cache, buffer_cache, query_cache),
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async_shaders(emu_window_) {
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if (device.UseAsynchronousShaders()) {
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@ -701,6 +701,10 @@ bool RasterizerOpenGL::AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surf
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return true;
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}
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Tegra::Engines::AccelerateDMAInterface& RasterizerOpenGL::AccessAccelerateDMA() {
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return accelerate_dma;
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}
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bool RasterizerOpenGL::AccelerateDisplay(const Tegra::FramebufferConfig& config,
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VAddr framebuffer_addr, u32 pixel_stride) {
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if (framebuffer_addr == 0) {
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@ -1396,4 +1400,11 @@ void RasterizerOpenGL::EndTransformFeedback() {
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glEndTransformFeedback();
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}
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AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_) : buffer_cache{buffer_cache_} {}
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bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) {
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std::scoped_lock lock{buffer_cache.mutex};
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return buffer_cache.DMACopy(src_address, dest_address, amount);
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}
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} // namespace OpenGL
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@ -19,6 +19,7 @@
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#include "common/common_types.h"
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#include "video_core/engines/const_buffer_info.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/rasterizer_accelerated.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/renderer_opengl/gl_buffer_cache.h"
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@ -58,6 +59,16 @@ struct BindlessSSBO {
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||||
};
|
||||
static_assert(sizeof(BindlessSSBO) * CHAR_BIT == 128);
|
||||
|
||||
class AccelerateDMA : public Tegra::Engines::AccelerateDMAInterface {
|
||||
public:
|
||||
explicit AccelerateDMA(BufferCache& buffer_cache);
|
||||
|
||||
bool BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) override;
|
||||
|
||||
private:
|
||||
BufferCache& buffer_cache;
|
||||
};
|
||||
|
||||
class RasterizerOpenGL : public VideoCore::RasterizerAccelerated {
|
||||
public:
|
||||
explicit RasterizerOpenGL(Core::Frontend::EmuWindow& emu_window_, Tegra::GPU& gpu_,
|
||||
@ -94,6 +105,7 @@ public:
|
||||
bool AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src,
|
||||
const Tegra::Engines::Fermi2D::Surface& dst,
|
||||
const Tegra::Engines::Fermi2D::Config& copy_config) override;
|
||||
Tegra::Engines::AccelerateDMAInterface& AccessAccelerateDMA() override;
|
||||
bool AccelerateDisplay(const Tegra::FramebufferConfig& config, VAddr framebuffer_addr,
|
||||
u32 pixel_stride) override;
|
||||
void LoadDiskResources(u64 title_id, std::stop_token stop_loading,
|
||||
@ -234,6 +246,7 @@ private:
|
||||
BufferCache buffer_cache;
|
||||
ShaderCacheOpenGL shader_cache;
|
||||
QueryCache query_cache;
|
||||
AccelerateDMA accelerate_dma;
|
||||
FenceManagerOpenGL fence_manager;
|
||||
|
||||
VideoCommon::Shader::AsyncShaders async_shaders;
|
||||
|
@ -251,7 +251,7 @@ RasterizerVulkan::RasterizerVulkan(Core::Frontend::EmuWindow& emu_window_, Tegra
|
||||
buffer_cache(*this, maxwell3d, kepler_compute, gpu_memory, cpu_memory_, buffer_cache_runtime),
|
||||
pipeline_cache(*this, gpu, maxwell3d, kepler_compute, gpu_memory, device, scheduler,
|
||||
descriptor_pool, update_descriptor_queue),
|
||||
query_cache{*this, maxwell3d, gpu_memory, device, scheduler},
|
||||
query_cache{*this, maxwell3d, gpu_memory, device, scheduler}, accelerate_dma{buffer_cache},
|
||||
fence_manager(*this, gpu, texture_cache, buffer_cache, query_cache, device, scheduler),
|
||||
wfi_event(device.GetLogical().CreateEvent()), async_shaders(emu_window_) {
|
||||
scheduler.SetQueryCache(query_cache);
|
||||
@ -660,6 +660,10 @@ bool RasterizerVulkan::AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surf
|
||||
return true;
|
||||
}
|
||||
|
||||
Tegra::Engines::AccelerateDMAInterface& RasterizerVulkan::AccessAccelerateDMA() {
|
||||
return accelerate_dma;
|
||||
}
|
||||
|
||||
bool RasterizerVulkan::AccelerateDisplay(const Tegra::FramebufferConfig& config,
|
||||
VAddr framebuffer_addr, u32 pixel_stride) {
|
||||
if (!framebuffer_addr) {
|
||||
@ -698,6 +702,13 @@ void RasterizerVulkan::FlushWork() {
|
||||
draw_counter = 0;
|
||||
}
|
||||
|
||||
AccelerateDMA::AccelerateDMA(BufferCache& buffer_cache_) : buffer_cache{buffer_cache_} {}
|
||||
|
||||
bool AccelerateDMA::BufferCopy(GPUVAddr src_address, GPUVAddr dest_address, u64 amount) {
|
||||
std::scoped_lock lock{buffer_cache.mutex};
|
||||
return buffer_cache.DMACopy(src_address, dest_address, amount);
|
||||
}
|
||||
|
||||
void RasterizerVulkan::SetupShaderDescriptors(
|
||||
const std::array<Shader*, Maxwell::MaxShaderProgram>& shaders, bool is_indexed) {
|
||||
image_view_indices.clear();
|
||||
|
@ -13,6 +13,7 @@
|
||||
#include <boost/container/static_vector.hpp>
|
||||
|
||||
#include "common/common_types.h"
|
||||
#include "video_core/engines/maxwell_dma.h"
|
||||
#include "video_core/rasterizer_accelerated.h"
|
||||
#include "video_core/rasterizer_interface.h"
|
||||
#include "video_core/renderer_vulkan/blit_image.h"
|
||||
@ -49,6 +50,16 @@ struct VKScreenInfo;
|
||||
|
||||
class StateTracker;
|
||||
|
||||
class AccelerateDMA : public Tegra::Engines::AccelerateDMAInterface {
|
||||
public:
|
||||
explicit AccelerateDMA(BufferCache& buffer_cache);
|
||||
|
||||
bool BufferCopy(GPUVAddr start_address, GPUVAddr end_address, u64 amount) override;
|
||||
|
||||
private:
|
||||
BufferCache& buffer_cache;
|
||||
};
|
||||
|
||||
class RasterizerVulkan final : public VideoCore::RasterizerAccelerated {
|
||||
public:
|
||||
explicit RasterizerVulkan(Core::Frontend::EmuWindow& emu_window_, Tegra::GPU& gpu_,
|
||||
@ -86,6 +97,7 @@ public:
|
||||
bool AccelerateSurfaceCopy(const Tegra::Engines::Fermi2D::Surface& src,
|
||||
const Tegra::Engines::Fermi2D::Surface& dst,
|
||||
const Tegra::Engines::Fermi2D::Config& copy_config) override;
|
||||
Tegra::Engines::AccelerateDMAInterface& AccessAccelerateDMA() override;
|
||||
bool AccelerateDisplay(const Tegra::FramebufferConfig& config, VAddr framebuffer_addr,
|
||||
u32 pixel_stride) override;
|
||||
|
||||
@ -186,6 +198,7 @@ private:
|
||||
BufferCache buffer_cache;
|
||||
VKPipelineCache pipeline_cache;
|
||||
VKQueryCache query_cache;
|
||||
AccelerateDMA accelerate_dma;
|
||||
VKFenceManager fence_manager;
|
||||
|
||||
vk::Event wfi_event;
|
||||
|
Loading…
Reference in New Issue
Block a user