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shader/shift: Implement SHR wrapped and clamped variants

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Nvidia defaults to wrapped shifts, but this is undefined behaviour on
OpenGL's spec. Explicitly mask/clamp according to what the guest shader
requires.
This commit is contained in:
ReinUsesLisp 2019-08-31 17:06:00 -03:00
parent 922c7f4e51
commit 77ef4fa907
2 changed files with 17 additions and 6 deletions
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4
src/video_core/engines/shader_bytecode.h
View File

@ -674,6 +674,10 @@ union Instruction {
BitField<48, 1, u64> is_signed; BitField<48, 1, u64> is_signed;
} shift; } shift;
union {
BitField<39, 1, u64> wrap;
} shr;
union { union {
BitField<39, 5, u64> shift_amount; BitField<39, 5, u64> shift_amount;
BitField<48, 1, u64> negate_b; BitField<48, 1, u64> negate_b;

19
src/video_core/shader/decode/shift.cpp
View File

@ -17,8 +17,8 @@ u32 ShaderIR::DecodeShift(NodeBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]}; const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr); const auto opcode = OpCode::Decode(instr);
const Node op_a = GetRegister(instr.gpr8); Node op_a = GetRegister(instr.gpr8);
const Node op_b = [&]() { Node op_b = [&]() {
if (instr.is_b_imm) { if (instr.is_b_imm) {
return Immediate(instr.alu.GetSignedImm20_20()); return Immediate(instr.alu.GetSignedImm20_20());
} else if (instr.is_b_gpr) { } else if (instr.is_b_gpr) {
@ -32,16 +32,23 @@ u32 ShaderIR::DecodeShift(NodeBlock& bb, u32 pc) {
case OpCode::Id::SHR_C: case OpCode::Id::SHR_C:
case OpCode::Id::SHR_R: case OpCode::Id::SHR_R:
case OpCode::Id::SHR_IMM: { case OpCode::Id::SHR_IMM: {
const Node value = SignedOperation(OperationCode::IArithmeticShiftRight, if (instr.shr.wrap) {
instr.shift.is_signed, PRECISE, op_a, op_b); op_b = Operation(OperationCode::UBitwiseAnd, std::move(op_b), Immediate(0x1f));
} else {
op_b = Operation(OperationCode::IMax, std::move(op_b), Immediate(0));
op_b = Operation(OperationCode::IMin, std::move(op_b), Immediate(31));
}
Node value = SignedOperation(OperationCode::IArithmeticShiftRight, instr.shift.is_signed,
std::move(op_a), std::move(op_b));
SetInternalFlagsFromInteger(bb, value, instr.generates_cc); SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
SetRegister(bb, instr.gpr0, value); SetRegister(bb, instr.gpr0, std::move(value));
break; break;
} }
case OpCode::Id::SHL_C: case OpCode::Id::SHL_C:
case OpCode::Id::SHL_R: case OpCode::Id::SHL_R:
case OpCode::Id::SHL_IMM: { case OpCode::Id::SHL_IMM: {
const Node value = Operation(OperationCode::ILogicalShiftLeft, PRECISE, op_a, op_b); const Node value = Operation(OperationCode::ILogicalShiftLeft, op_a, op_b);
SetInternalFlagsFromInteger(bb, value, instr.generates_cc); SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
SetRegister(bb, instr.gpr0, value); SetRegister(bb, instr.gpr0, value);
break; break;