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shader: Implement R2P
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924f0a9149
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@ -94,6 +94,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/logic_operation_three_input.cpp
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frontend/maxwell/translate/impl/move_predicate_to_register.cpp
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frontend/maxwell/translate/impl/move_register.cpp
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frontend/maxwell/translate/impl/move_register_to_predicate.cpp
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frontend/maxwell/translate/impl/move_special_register.cpp
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frontend/maxwell/translate/impl/not_implemented.cpp
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frontend/maxwell/translate/impl/predicate_set_predicate.cpp
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@ -120,6 +120,7 @@ void EmitCompositeExtractF64x4(EmitContext& ctx);
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Id EmitCompositeInsertF64x2(EmitContext& ctx, Id composite, Id object, u32 index);
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Id EmitCompositeInsertF64x3(EmitContext& ctx, Id composite, Id object, u32 index);
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Id EmitCompositeInsertF64x4(EmitContext& ctx, Id composite, Id object, u32 index);
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Id EmitSelectU1(EmitContext& ctx, Id cond, Id true_value, Id false_value);
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Id EmitSelectU8(EmitContext& ctx, Id cond, Id true_value, Id false_value);
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Id EmitSelectU16(EmitContext& ctx, Id cond, Id true_value, Id false_value);
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Id EmitSelectU32(EmitContext& ctx, Id cond, Id true_value, Id false_value);
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@ -242,7 +243,7 @@ Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b);
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Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b);
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Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count);
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Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count);
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Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
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Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count);
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Id EmitBitReverse32(EmitContext& ctx, Id value);
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Id EmitBitCount32(EmitContext& ctx, Id value);
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Id EmitBitwiseNot32(EmitContext& ctx, Id value);
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@ -114,8 +114,13 @@ Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count) {
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return ctx.OpBitFieldSExtract(ctx.U32[1], base, offset, count);
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}
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Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) {
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return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count);
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Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count) {
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const Id result{ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count)};
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if (IR::Inst* const zero{inst->GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp)}) {
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zero->SetDefinition(ctx.OpIEqual(ctx.U1, result, ctx.u32_zero_value));
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zero->Invalidate();
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}
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return result;
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}
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Id EmitBitReverse32(EmitContext& ctx, Id value) {
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@ -6,6 +6,10 @@
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namespace Shader::Backend::SPIRV {
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Id EmitSelectU1(EmitContext& ctx, Id cond, Id true_value, Id false_value) {
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return ctx.OpSelect(ctx.U1, cond, true_value, false_value);
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}
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Id EmitSelectU8([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Id cond,
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[[maybe_unused]] Id true_value, [[maybe_unused]] Id false_value) {
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throw NotImplementedException("SPIR-V Instruction");
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@ -412,6 +412,8 @@ Value IREmitter::Select(const U1& condition, const Value& true_value, const Valu
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throw InvalidArgument("Mismatching types {} and {}", true_value.Type(), false_value.Type());
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}
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switch (true_value.Type()) {
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case Type::U1:
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return Inst(Opcode::SelectU1, condition, true_value, false_value);
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case Type::U8:
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return Inst(Opcode::SelectU8, condition, true_value, false_value);
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case Type::U16:
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@ -115,6 +115,7 @@ OPCODE(CompositeInsertF64x3, F64x3, F64x
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OPCODE(CompositeInsertF64x4, F64x4, F64x4, F64, U32, )
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// Select operations
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OPCODE(SelectU1, U1, U1, U1, U1, )
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OPCODE(SelectU8, U8, U1, U8, U8, )
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OPCODE(SelectU16, U16, U1, U16, U16, )
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OPCODE(SelectU32, U32, U1, U32, U32, )
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@ -0,0 +1,71 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class Mode : u64 {
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PR,
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CC,
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};
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void SetFlag(IR::IREmitter& ir, const IR::U1& inv_mask_bit, const IR::U1& src_bit, u32 index) {
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switch (index) {
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case 0:
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return ir.SetZFlag(IR::U1{ir.Select(inv_mask_bit, ir.GetZFlag(), src_bit)});
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case 1:
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return ir.SetSFlag(IR::U1{ir.Select(inv_mask_bit, ir.GetSFlag(), src_bit)});
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case 2:
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return ir.SetCFlag(IR::U1{ir.Select(inv_mask_bit, ir.GetCFlag(), src_bit)});
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case 3:
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return ir.SetOFlag(IR::U1{ir.Select(inv_mask_bit, ir.GetOFlag(), src_bit)});
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default:
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throw LogicError("Unreachable R2P index");
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}
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}
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void R2P(TranslatorVisitor& v, u64 insn, const IR::U32& mask) {
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union {
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u64 raw;
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BitField<8, 8, IR::Reg> src_reg;
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BitField<40, 1, Mode> mode;
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BitField<41, 2, u64> byte_selector;
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} const r2p{insn};
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const IR::U32 src{v.X(r2p.src_reg)};
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const IR::U32 count{v.ir.Imm32(1)};
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const bool pr_mode{r2p.mode == Mode::PR};
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const u32 num_items{pr_mode ? 7U : 4U};
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const u32 offset_base{static_cast<u32>(r2p.byte_selector) * 8};
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for (u32 index = 0; index < num_items; ++index) {
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const IR::U32 offset{v.ir.Imm32(offset_base + index)};
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const IR::U1 src_zero{v.ir.GetZeroFromOp(v.ir.BitFieldExtract(src, offset, count, false))};
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const IR::U1 src_bit{v.ir.LogicalNot(src_zero)};
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const IR::U32 mask_bfe{v.ir.BitFieldExtract(mask, v.ir.Imm32(index), count, false)};
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const IR::U1 inv_mask_bit{v.ir.GetZeroFromOp(mask_bfe)};
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if (pr_mode) {
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const IR::Pred pred{index};
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v.ir.SetPred(pred, IR::U1{v.ir.Select(inv_mask_bit, v.ir.GetPred(pred), src_bit)});
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} else {
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SetFlag(v.ir, inv_mask_bit, src_bit, index);
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}
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}
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}
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} // Anonymous namespace
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void TranslatorVisitor::R2P_reg(u64 insn) {
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R2P(*this, insn, GetReg20(insn));
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}
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void TranslatorVisitor::R2P_cbuf(u64 insn) {
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R2P(*this, insn, GetCbuf(insn));
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}
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void TranslatorVisitor::R2P_imm(u64 insn) {
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R2P(*this, insn, GetImm20(insn));
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}
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} // namespace Shader::Maxwell
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@ -513,18 +513,6 @@ void TranslatorVisitor::R2B(u64) {
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ThrowNotImplemented(Opcode::R2B);
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}
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void TranslatorVisitor::R2P_reg(u64) {
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ThrowNotImplemented(Opcode::R2P_reg);
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}
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void TranslatorVisitor::R2P_cbuf(u64) {
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ThrowNotImplemented(Opcode::R2P_cbuf);
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}
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void TranslatorVisitor::R2P_imm(u64) {
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ThrowNotImplemented(Opcode::R2P_imm);
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}
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void TranslatorVisitor::RAM(u64) {
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ThrowNotImplemented(Opcode::RAM);
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}
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