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Merge pull request #618 from Subv/clear_used_buffers
GPU: Only configure the used framebuffers during clear.
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commit
81a44d38ee
@ -297,7 +297,8 @@ bool RasterizerOpenGL::AccelerateDrawBatch(bool is_indexed) {
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return true;
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}
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std::pair<Surface, Surface> RasterizerOpenGL::ConfigureFramebuffers() {
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std::pair<Surface, Surface> RasterizerOpenGL::ConfigureFramebuffers(bool using_color_fb,
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bool using_depth_fb) {
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const auto& regs = Core::System().GetInstance().GPU().Maxwell3D().regs;
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// Sync the depth test state before configuring the framebuffer surfaces.
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@ -306,9 +307,6 @@ std::pair<Surface, Surface> RasterizerOpenGL::ConfigureFramebuffers() {
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// TODO(bunnei): Implement this
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const bool has_stencil = false;
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const bool using_color_fb = true;
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const bool using_depth_fb = regs.zeta.Address() != 0;
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const MathUtil::Rectangle<s32> viewport_rect{regs.viewport_transform[0].GetRect()};
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const bool write_color_fb =
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@ -358,18 +356,25 @@ std::pair<Surface, Surface> RasterizerOpenGL::ConfigureFramebuffers() {
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void RasterizerOpenGL::Clear() {
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const auto& regs = Core::System().GetInstance().GPU().Maxwell3D().regs;
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bool use_color_fb = false;
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bool use_depth_fb = false;
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GLbitfield clear_mask = 0;
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if (regs.clear_buffers.R && regs.clear_buffers.G && regs.clear_buffers.B &&
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regs.clear_buffers.A) {
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clear_mask |= GL_COLOR_BUFFER_BIT;
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use_color_fb = true;
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}
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if (regs.clear_buffers.Z)
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if (regs.clear_buffers.Z) {
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clear_mask |= GL_DEPTH_BUFFER_BIT;
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use_depth_fb = true;
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}
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if (clear_mask == 0)
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return;
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auto [dirty_color_surface, dirty_depth_surface] = ConfigureFramebuffers();
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auto [dirty_color_surface, dirty_depth_surface] =
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ConfigureFramebuffers(use_color_fb, use_depth_fb);
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// TODO(Subv): Support clearing only partial colors.
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glClearColor(regs.clear_color[0], regs.clear_color[1], regs.clear_color[2],
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@ -394,7 +399,8 @@ void RasterizerOpenGL::DrawArrays() {
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MICROPROFILE_SCOPE(OpenGL_Drawing);
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const auto& regs = Core::System().GetInstance().GPU().Maxwell3D().regs;
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auto [dirty_color_surface, dirty_depth_surface] = ConfigureFramebuffers();
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auto [dirty_color_surface, dirty_depth_surface] =
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ConfigureFramebuffers(true, regs.zeta.Address() != 0);
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SyncBlendState();
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SyncCullMode();
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@ -85,7 +85,7 @@ private:
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/// Configures the color and depth framebuffer states and returns the dirty <Color, Depth>
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/// surfaces if writing was enabled.
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std::pair<Surface, Surface> ConfigureFramebuffers();
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std::pair<Surface, Surface> ConfigureFramebuffers(bool using_color_fb, bool using_depth_fb);
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/// Binds the framebuffer color and depth surface
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void BindFramebufferSurfaces(const Surface& color_surface, const Surface& depth_surface,
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@ -65,6 +65,25 @@ struct FormatTuple {
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return params;
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}
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/*static*/ SurfaceParams SurfaceParams::CreateForDepthBuffer(
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const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& config, Tegra::GPUVAddr zeta_address,
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Tegra::DepthFormat format) {
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SurfaceParams params{};
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params.addr = zeta_address;
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params.is_tiled = true;
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params.block_height = Tegra::Texture::TICEntry::DefaultBlockHeight;
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params.pixel_format = PixelFormatFromDepthFormat(format);
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params.component_type = ComponentTypeFromDepthFormat(format);
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params.type = GetFormatType(params.pixel_format);
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params.size_in_bytes = params.SizeInBytes();
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params.width = config.width;
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params.height = config.height;
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params.unaligned_height = config.height;
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params.size_in_bytes = params.SizeInBytes();
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return params;
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}
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static constexpr std::array<FormatTuple, SurfaceParams::MaxPixelFormat> tex_format_tuples = {{
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{GL_RGBA8, GL_RGBA, GL_UNSIGNED_INT_8_8_8_8_REV, ComponentType::UNorm, false}, // ABGR8
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{GL_RGB, GL_RGB, GL_UNSIGNED_SHORT_5_6_5_REV, ComponentType::UNorm, false}, // B5G6R5
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@ -461,15 +480,16 @@ SurfaceSurfaceRect_Tuple RasterizerCacheOpenGL::GetFramebufferSurfaces(
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LOG_WARNING(Render_OpenGL, "hard-coded for render target 0!");
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// get color and depth surfaces
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const SurfaceParams color_params{SurfaceParams::CreateForFramebuffer(regs.rt[0])};
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SurfaceParams depth_params{color_params};
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SurfaceParams color_params{};
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SurfaceParams depth_params{};
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if (using_color_fb) {
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color_params = SurfaceParams::CreateForFramebuffer(regs.rt[0]);
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}
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if (using_depth_fb) {
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depth_params.addr = regs.zeta.Address();
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depth_params.pixel_format = SurfaceParams::PixelFormatFromDepthFormat(regs.zeta.format);
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depth_params.component_type = SurfaceParams::ComponentTypeFromDepthFormat(regs.zeta.format);
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depth_params.type = SurfaceParams::GetFormatType(depth_params.pixel_format);
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depth_params.size_in_bytes = depth_params.SizeInBytes();
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depth_params =
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SurfaceParams::CreateForDepthBuffer(regs.rt[0], regs.zeta.Address(), regs.zeta.format);
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}
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MathUtil::Rectangle<u32> color_rect{};
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@ -326,13 +326,18 @@ struct SurfaceParams {
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return addr <= (region_addr + region_size) && region_addr <= (addr + size_in_bytes);
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}
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/// Creates SurfaceParams from a texture configation
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/// Creates SurfaceParams from a texture configuration
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static SurfaceParams CreateForTexture(const Tegra::Texture::FullTextureInfo& config);
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/// Creates SurfaceParams from a framebuffer configation
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/// Creates SurfaceParams from a framebuffer configuration
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static SurfaceParams CreateForFramebuffer(
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const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& config);
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/// Creates SurfaceParams for a depth buffer configuration
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static SurfaceParams CreateForDepthBuffer(
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const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& config,
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Tegra::GPUVAddr zeta_address, Tegra::DepthFormat format);
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Tegra::GPUVAddr addr;
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bool is_tiled;
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u32 block_height;
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