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Merge pull request #2812 from ReinUsesLisp/f2i-selector
shader_ir/conversion: Implement F2I and F2F F16 selector
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commit
81fbc5370d
@ -1020,7 +1020,6 @@ union Instruction {
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} iset;
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} iset;
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union {
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union {
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BitField<41, 2, u64> selector; // i2i and i2f only
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BitField<45, 1, u64> negate_a;
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BitField<45, 1, u64> negate_a;
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BitField<49, 1, u64> abs_a;
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BitField<49, 1, u64> abs_a;
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BitField<10, 2, Register::Size> src_size;
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BitField<10, 2, Register::Size> src_size;
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@ -1046,6 +1045,13 @@ union Instruction {
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}
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}
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} f2f;
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} f2f;
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union {
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BitField<41, 2, u64> selector;
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} int_src;
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union {
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BitField<41, 1, u64> selector;
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} float_src;
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} conversion;
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} conversion;
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union {
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union {
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@ -14,6 +14,12 @@ using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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using Tegra::Shader::Register;
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namespace {
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constexpr OperationCode GetFloatSelector(u64 selector) {
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return selector == 0 ? OperationCode::FCastHalf0 : OperationCode::FCastHalf1;
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}
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} // Anonymous namespace
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u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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const auto opcode = OpCode::Decode(instr);
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@ -22,7 +28,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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case OpCode::Id::I2I_R:
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case OpCode::Id::I2I_R:
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case OpCode::Id::I2I_C:
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case OpCode::Id::I2I_C:
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case OpCode::Id::I2I_IMM: {
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case OpCode::Id::I2I_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.selector);
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UNIMPLEMENTED_IF(instr.conversion.int_src.selector != 0);
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UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.alu.saturate_d);
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UNIMPLEMENTED_IF(instr.alu.saturate_d);
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@ -57,8 +63,8 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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case OpCode::Id::I2F_R:
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case OpCode::Id::I2F_R:
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case OpCode::Id::I2F_C:
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case OpCode::Id::I2F_C:
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case OpCode::Id::I2F_IMM: {
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case OpCode::Id::I2F_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.int_src.selector != 0);
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UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
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UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
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UNIMPLEMENTED_IF(instr.conversion.selector);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in I2F is not implemented");
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"Condition codes generation in I2F is not implemented");
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@ -113,8 +119,10 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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}();
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}();
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if (instr.conversion.src_size == Register::Size::Short) {
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if (instr.conversion.src_size == Register::Size::Short) {
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// TODO: figure where extract is sey in the encoding
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value = Operation(GetFloatSelector(instr.conversion.float_src.selector), NO_PRECISE,
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value = Operation(OperationCode::FCastHalf0, PRECISE, value);
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std::move(value));
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} else {
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ASSERT(instr.conversion.float_src.selector == 0);
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}
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}
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value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
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value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
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@ -169,8 +177,10 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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}();
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}();
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if (instr.conversion.src_size == Register::Size::Short) {
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if (instr.conversion.src_size == Register::Size::Short) {
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// TODO: figure where extract is sey in the encoding
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value = Operation(GetFloatSelector(instr.conversion.float_src.selector), NO_PRECISE,
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value = Operation(OperationCode::FCastHalf0, PRECISE, value);
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std::move(value));
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} else {
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ASSERT(instr.conversion.float_src.selector == 0);
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}
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}
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value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
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value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
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