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Merge pull request #1512 from ReinUsesLisp/brk
gl_shader_decompiler: Implement PBK and BRK
This commit is contained in:
commit
848a49112a
@ -1213,11 +1213,13 @@ public:
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KIL,
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KIL,
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SSY,
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SSY,
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SYNC,
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SYNC,
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BRK,
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DEPBAR,
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DEPBAR,
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BFE_C,
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BFE_C,
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BFE_R,
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BFE_R,
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BFE_IMM,
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BFE_IMM,
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BRA,
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BRA,
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PBK,
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LD_A,
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LD_A,
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LD_C,
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LD_C,
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ST_A,
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ST_A,
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@ -1374,7 +1376,7 @@ public:
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/// conditionally executed).
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/// conditionally executed).
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static bool IsPredicatedInstruction(Id opcode) {
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static bool IsPredicatedInstruction(Id opcode) {
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// TODO(Subv): Add the rest of unpredicated instructions.
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// TODO(Subv): Add the rest of unpredicated instructions.
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return opcode != Id::SSY;
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return opcode != Id::SSY && opcode != Id::PBK;
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}
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}
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class Matcher {
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class Matcher {
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@ -1470,9 +1472,11 @@ private:
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#define INST(bitstring, op, type, name) Detail::GetMatcher(bitstring, op, type, name)
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#define INST(bitstring, op, type, name) Detail::GetMatcher(bitstring, op, type, name)
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
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INST("111000101001----", Id::SSY, Type::Flow, "SSY"),
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INST("111000101001----", Id::SSY, Type::Flow, "SSY"),
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INST("111000101010----", Id::PBK, Type::Flow, "PBK"),
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INST("111000100100----", Id::BRA, Type::Flow, "BRA"),
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INST("111000100100----", Id::BRA, Type::Flow, "BRA"),
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INST("1111000011111---", Id::SYNC, Type::Flow, "SYNC"),
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INST("111000110100---", Id::BRK, Type::Flow, "BRK"),
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INST("1111000011110---", Id::DEPBAR, Type::Synch, "DEPBAR"),
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INST("1111000011110---", Id::DEPBAR, Type::Synch, "DEPBAR"),
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INST("1111000011111---", Id::SYNC, Type::Synch, "SYNC"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111110010---", Id::LD_C, Type::Memory, "LD_C"),
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INST("1110111110010---", Id::LD_C, Type::Memory, "LD_C"),
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INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"),
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INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"),
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@ -1610,4 +1614,4 @@ private:
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}
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}
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};
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};
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} // namespace Tegra::Shader
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} // namespace Tegra::Shader
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@ -163,10 +163,11 @@ private:
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const ExitMethod jmp = Scan(target, end, labels);
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const ExitMethod jmp = Scan(target, end, labels);
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return exit_method = ParallelExit(no_jmp, jmp);
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return exit_method = ParallelExit(no_jmp, jmp);
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}
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}
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case OpCode::Id::SSY: {
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case OpCode::Id::SSY:
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// The SSY instruction uses a similar encoding as the BRA instruction.
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case OpCode::Id::PBK: {
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// The SSY and PBK use a similar encoding as the BRA instruction.
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ASSERT_MSG(instr.bra.constant_buffer == 0,
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ASSERT_MSG(instr.bra.constant_buffer == 0,
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"Constant buffer SSY is not supported");
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"Constant buffer branching is not supported");
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const u32 target = offset + instr.bra.GetBranchTarget();
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const u32 target = offset + instr.bra.GetBranchTarget();
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labels.insert(target);
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labels.insert(target);
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// Continue scanning for an exit method.
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// Continue scanning for an exit method.
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@ -1233,27 +1234,27 @@ private:
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}
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}
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/*
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/*
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* Emits code to push the input target address to the SSY address stack, incrementing the stack
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* Emits code to push the input target address to the flow address stack, incrementing the stack
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* top.
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* top.
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*/
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*/
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void EmitPushToSSYStack(u32 target) {
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void EmitPushToFlowStack(u32 target) {
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shader.AddLine('{');
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shader.AddLine('{');
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++shader.scope;
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++shader.scope;
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shader.AddLine("ssy_stack[ssy_stack_top] = " + std::to_string(target) + "u;");
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shader.AddLine("flow_stack[flow_stack_top] = " + std::to_string(target) + "u;");
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shader.AddLine("ssy_stack_top++;");
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shader.AddLine("flow_stack_top++;");
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--shader.scope;
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--shader.scope;
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shader.AddLine('}');
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shader.AddLine('}');
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}
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}
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/*
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/*
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* Emits code to pop an address from the SSY address stack, setting the jump address to the
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* Emits code to pop an address from the flow address stack, setting the jump address to the
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* popped address and decrementing the stack top.
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* popped address and decrementing the stack top.
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*/
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*/
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void EmitPopFromSSYStack() {
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void EmitPopFromFlowStack() {
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shader.AddLine('{');
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shader.AddLine('{');
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++shader.scope;
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++shader.scope;
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shader.AddLine("ssy_stack_top--;");
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shader.AddLine("flow_stack_top--;");
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shader.AddLine("jmp_to = ssy_stack[ssy_stack_top];");
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shader.AddLine("jmp_to = flow_stack[flow_stack_top];");
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shader.AddLine("break;");
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shader.AddLine("break;");
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--shader.scope;
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--shader.scope;
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shader.AddLine('}');
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shader.AddLine('}');
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@ -3265,16 +3266,32 @@ private:
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// The SSY opcode tells the GPU where to re-converge divergent execution paths, it
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// The SSY opcode tells the GPU where to re-converge divergent execution paths, it
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// sets the target of the jump that the SYNC instruction will make. The SSY opcode
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// sets the target of the jump that the SYNC instruction will make. The SSY opcode
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// has a similar structure to the BRA opcode.
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// has a similar structure to the BRA opcode.
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ASSERT_MSG(instr.bra.constant_buffer == 0, "Constant buffer SSY is not supported");
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ASSERT_MSG(instr.bra.constant_buffer == 0, "Constant buffer flow is not supported");
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const u32 target = offset + instr.bra.GetBranchTarget();
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const u32 target = offset + instr.bra.GetBranchTarget();
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EmitPushToSSYStack(target);
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EmitPushToFlowStack(target);
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break;
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}
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case OpCode::Id::PBK: {
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// PBK pushes to a stack the address where BRK will jump to. This shares stack with
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// SSY but using SYNC on a PBK address will kill the shader execution. We don't
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// emulate this because it's very unlikely a driver will emit such invalid shader.
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ASSERT_MSG(instr.bra.constant_buffer == 0, "Constant buffer PBK is not supported");
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const u32 target = offset + instr.bra.GetBranchTarget();
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EmitPushToFlowStack(target);
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break;
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break;
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}
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}
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case OpCode::Id::SYNC: {
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case OpCode::Id::SYNC: {
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// The SYNC opcode jumps to the address previously set by the SSY opcode
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// The SYNC opcode jumps to the address previously set by the SSY opcode
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ASSERT(instr.flow.cond == Tegra::Shader::FlowCondition::Always);
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ASSERT(instr.flow.cond == Tegra::Shader::FlowCondition::Always);
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EmitPopFromSSYStack();
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EmitPopFromFlowStack();
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break;
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}
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case OpCode::Id::BRK: {
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// The BRK opcode jumps to the address previously set by the PBK opcode
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ASSERT(instr.flow.cond == Tegra::Shader::FlowCondition::Always);
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EmitPopFromFlowStack();
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break;
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break;
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}
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}
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case OpCode::Id::DEPBAR: {
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case OpCode::Id::DEPBAR: {
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@ -3428,11 +3445,11 @@ private:
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labels.insert(subroutine.begin);
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labels.insert(subroutine.begin);
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shader.AddLine("uint jmp_to = " + std::to_string(subroutine.begin) + "u;");
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shader.AddLine("uint jmp_to = " + std::to_string(subroutine.begin) + "u;");
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// TODO(Subv): Figure out the actual depth of the SSY stack, for now it seems
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// TODO(Subv): Figure out the actual depth of the flow stack, for now it seems
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// unlikely that shaders will use 20 nested SSYs.
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// unlikely that shaders will use 20 nested SSYs and PBKs.
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constexpr u32 SSY_STACK_SIZE = 20;
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constexpr u32 FLOW_STACK_SIZE = 20;
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shader.AddLine("uint ssy_stack[" + std::to_string(SSY_STACK_SIZE) + "];");
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shader.AddLine("uint flow_stack[" + std::to_string(FLOW_STACK_SIZE) + "];");
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shader.AddLine("uint ssy_stack_top = 0u;");
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shader.AddLine("uint flow_stack_top = 0u;");
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shader.AddLine("while (true) {");
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shader.AddLine("while (true) {");
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++shader.scope;
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++shader.scope;
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