mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-08-20 13:43:22 +02:00
video_core: Implement vulkan QuadStrip topology
This commit is contained in:
parent
8ef9075b1b
commit
86d5b4e556
@ -666,9 +666,10 @@ void BufferCache<P>::BindHostGeometryBuffers(bool is_indexed) {
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BindHostIndexBuffer();
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} else if constexpr (!HAS_FULL_INDEX_AND_PRIMITIVE_SUPPORT) {
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const auto& draw_state = maxwell3d->draw_manager->GetDrawState();
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if (draw_state.topology == Maxwell::PrimitiveTopology::Quads) {
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runtime.BindQuadArrayIndexBuffer(draw_state.vertex_buffer.first,
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draw_state.vertex_buffer.count);
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if (draw_state.topology == Maxwell::PrimitiveTopology::Quads ||
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draw_state.topology == Maxwell::PrimitiveTopology::QuadStrip) {
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runtime.BindQuadIndexBuffer(draw_state.topology, draw_state.vertex_buffer.first,
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draw_state.vertex_buffer.count);
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}
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}
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BindHostVertexBuffers();
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@ -16,6 +16,7 @@ layout (std430, set = 0, binding = 1) writeonly buffer OutputBuffer {
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layout (push_constant) uniform PushConstants {
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uint base_vertex;
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int index_shift; // 0: uint8, 1: uint16, 2: uint32
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int is_strip; // 0: quads 1: quadstrip
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};
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void main() {
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@ -28,9 +29,10 @@ void main() {
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int flipped_shift = 2 - index_shift;
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int mask = (1 << flipped_shift) - 1;
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const int quad_swizzle[6] = int[](0, 1, 2, 0, 2, 3);
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const int quads_swizzle[6] = int[](0, 1, 2, 0, 2, 3);
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const int quad_strip_swizzle[6] = int[](0, 3, 1, 0, 2, 3);
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for (uint vertex = 0; vertex < 6; ++vertex) {
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int offset = primitive * 4 + quad_swizzle[vertex];
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int offset = (is_strip == 0 ? primitive * 4 + quads_swizzle[vertex] : primitive * 2 + quad_strip_swizzle[vertex]);
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int int_offset = offset >> flipped_shift;
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int bit_offset = (offset & mask) * index_size;
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uint packed_input = input_indexes[int_offset];
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@ -310,7 +310,9 @@ VkPrimitiveTopology PrimitiveTopology([[maybe_unused]] const Device& device,
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case Maxwell::PrimitiveTopology::TriangleFan:
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return VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN;
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case Maxwell::PrimitiveTopology::Quads:
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// TODO(Rodrigo): Use VK_PRIMITIVE_TOPOLOGY_QUAD_LIST_EXT whenever it releases
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case Maxwell::PrimitiveTopology::QuadStrip:
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// TODO: Use VK_PRIMITIVE_TOPOLOGY_QUAD_LIST_EXT/VK_PRIMITIVE_TOPOLOGY_QUAD_STRIP_EXT
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// whenever it releases
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return VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST;
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case Maxwell::PrimitiveTopology::Patches:
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return VK_PRIMITIVE_TOPOLOGY_PATCH_LIST;
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@ -51,15 +51,6 @@ size_t BytesPerIndex(VkIndexType index_type) {
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}
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}
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template <typename T>
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std::array<T, 6> MakeQuadIndices(u32 quad, u32 first) {
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std::array<T, 6> indices{0, 1, 2, 0, 2, 3};
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for (T& index : indices) {
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index = static_cast<T>(first + index + quad * 4);
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}
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return indices;
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}
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vk::Buffer CreateBuffer(const Device& device, u64 size) {
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VkBufferUsageFlags flags =
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VK_BUFFER_USAGE_TRANSFER_SRC_BIT | VK_BUFFER_USAGE_TRANSFER_DST_BIT |
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@ -123,6 +114,187 @@ VkBufferView Buffer::View(u32 offset, u32 size, VideoCore::Surface::PixelFormat
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return *views.back().handle;
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}
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class QuadIndexBuffer {
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public:
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QuadIndexBuffer(const Device& device_, MemoryAllocator& memory_allocator_,
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Scheduler& scheduler_, StagingBufferPool& staging_pool_)
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: device{device_}, memory_allocator{memory_allocator_}, scheduler{scheduler_},
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staging_pool{staging_pool_} {}
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virtual ~QuadIndexBuffer() = default;
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void UpdateBuffer(u32 num_indices_) {
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if (num_indices_ <= num_indices) {
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return;
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}
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scheduler.Finish();
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num_indices = num_indices_;
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index_type = IndexTypeFromNumElements(device, num_indices);
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const u32 num_quads = GetQuadsNum(num_indices);
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const u32 num_triangle_indices = num_quads * 6;
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const u32 num_first_offset_copies = 4;
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const size_t bytes_per_index = BytesPerIndex(index_type);
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const size_t size_bytes = num_triangle_indices * bytes_per_index * num_first_offset_copies;
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buffer = device.GetLogical().CreateBuffer(VkBufferCreateInfo{
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.sType = VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.size = size_bytes,
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.usage = VK_BUFFER_USAGE_INDEX_BUFFER_BIT | VK_BUFFER_USAGE_TRANSFER_DST_BIT,
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.sharingMode = VK_SHARING_MODE_EXCLUSIVE,
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.queueFamilyIndexCount = 0,
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.pQueueFamilyIndices = nullptr,
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});
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if (device.HasDebuggingToolAttached()) {
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buffer.SetObjectNameEXT("Quad LUT");
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}
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memory_commit = memory_allocator.Commit(buffer, MemoryUsage::DeviceLocal);
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const StagingBufferRef staging = staging_pool.Request(size_bytes, MemoryUsage::Upload);
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u8* staging_data = staging.mapped_span.data();
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const size_t quad_size = bytes_per_index * 6;
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for (u32 first = 0; first < num_first_offset_copies; ++first) {
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for (u32 quad = 0; quad < num_quads; ++quad) {
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MakeAndUpdateIndices(staging_data, quad_size, quad, first);
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staging_data += quad_size;
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}
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}
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scheduler.RequestOutsideRenderPassOperationContext();
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scheduler.Record([src_buffer = staging.buffer, src_offset = staging.offset,
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dst_buffer = *buffer, size_bytes](vk::CommandBuffer cmdbuf) {
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const VkBufferCopy copy{
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.srcOffset = src_offset,
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.dstOffset = 0,
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.size = size_bytes,
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};
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const VkBufferMemoryBarrier write_barrier{
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.sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER,
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.pNext = nullptr,
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.srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT,
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.dstAccessMask = VK_ACCESS_INDEX_READ_BIT,
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.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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.buffer = dst_buffer,
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.offset = 0,
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.size = size_bytes,
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};
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cmdbuf.CopyBuffer(src_buffer, dst_buffer, copy);
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cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_TRANSFER_BIT,
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VK_PIPELINE_STAGE_VERTEX_INPUT_BIT, 0, write_barrier);
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});
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}
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void BindBuffer(u32 first) {
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const VkIndexType index_type_ = index_type;
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const size_t sub_first_offset = static_cast<size_t>(first % 4) * GetQuadsNum(num_indices);
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const size_t offset =
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(sub_first_offset + GetQuadsNum(first)) * 6ULL * BytesPerIndex(index_type);
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scheduler.Record([buffer = *buffer, index_type_, offset](vk::CommandBuffer cmdbuf) {
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cmdbuf.BindIndexBuffer(buffer, offset, index_type_);
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});
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}
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protected:
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virtual u32 GetQuadsNum(u32 num_indices) const = 0;
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virtual void MakeAndUpdateIndices(u8* staging_data, size_t quad_size, u32 quad, u32 first) = 0;
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const Device& device;
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MemoryAllocator& memory_allocator;
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Scheduler& scheduler;
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StagingBufferPool& staging_pool;
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vk::Buffer buffer{};
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MemoryCommit memory_commit{};
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VkIndexType index_type{};
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u32 num_indices = 0;
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};
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class QuadArrayIndexBuffer : public QuadIndexBuffer {
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public:
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QuadArrayIndexBuffer(const Device& device_, MemoryAllocator& memory_allocator_,
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Scheduler& scheduler_, StagingBufferPool& staging_pool_)
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: QuadIndexBuffer(device_, memory_allocator_, scheduler_, staging_pool_) {}
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~QuadArrayIndexBuffer() = default;
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private:
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u32 GetQuadsNum(u32 num_indices_) const override {
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return num_indices_ / 4;
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}
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template <typename T>
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static std::array<T, 6> MakeIndices(u32 quad, u32 first) {
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std::array<T, 6> indices{0, 1, 2, 0, 2, 3};
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for (T& index : indices) {
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index = static_cast<T>(first + index + quad * 4);
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}
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return indices;
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}
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void MakeAndUpdateIndices(u8* staging_data, size_t quad_size, u32 quad, u32 first) {
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switch (index_type) {
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case VK_INDEX_TYPE_UINT8_EXT:
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std::memcpy(staging_data, MakeIndices<u8>(quad, first).data(), quad_size);
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break;
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case VK_INDEX_TYPE_UINT16:
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std::memcpy(staging_data, MakeIndices<u16>(quad, first).data(), quad_size);
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break;
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case VK_INDEX_TYPE_UINT32:
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std::memcpy(staging_data, MakeIndices<u32>(quad, first).data(), quad_size);
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break;
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default:
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ASSERT(false);
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break;
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}
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}
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};
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class QuadStripIndexBuffer : public QuadIndexBuffer {
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public:
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QuadStripIndexBuffer(const Device& device_, MemoryAllocator& memory_allocator_,
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Scheduler& scheduler_, StagingBufferPool& staging_pool_)
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: QuadIndexBuffer(device_, memory_allocator_, scheduler_, staging_pool_) {}
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~QuadStripIndexBuffer() = default;
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private:
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u32 GetQuadsNum(u32 num_indices_) const override {
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return num_indices_ >= 4 ? (num_indices_ - 2) / 2 : 0;
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}
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template <typename T>
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static std::array<T, 6> MakeIndices(u32 quad, u32 first) {
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std::array<T, 6> indices{0, 3, 1, 0, 2, 3};
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for (T& index : indices) {
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index = static_cast<T>(first + index + quad * 2);
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}
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return indices;
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}
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void MakeAndUpdateIndices(u8* staging_data, size_t quad_size, u32 quad, u32 first) {
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switch (index_type) {
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case VK_INDEX_TYPE_UINT8_EXT:
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std::memcpy(staging_data, MakeIndices<u8>(quad, first).data(), quad_size);
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break;
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case VK_INDEX_TYPE_UINT16:
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std::memcpy(staging_data, MakeIndices<u16>(quad, first).data(), quad_size);
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break;
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case VK_INDEX_TYPE_UINT32:
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std::memcpy(staging_data, MakeIndices<u32>(quad, first).data(), quad_size);
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break;
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default:
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ASSERT(false);
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break;
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}
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}
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};
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BufferCacheRuntime::BufferCacheRuntime(const Device& device_, MemoryAllocator& memory_allocator_,
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Scheduler& scheduler_, StagingBufferPool& staging_pool_,
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UpdateDescriptorQueue& update_descriptor_queue_,
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@ -130,7 +302,12 @@ BufferCacheRuntime::BufferCacheRuntime(const Device& device_, MemoryAllocator& m
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: device{device_}, memory_allocator{memory_allocator_}, scheduler{scheduler_},
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staging_pool{staging_pool_}, update_descriptor_queue{update_descriptor_queue_},
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uint8_pass(device, scheduler, descriptor_pool, staging_pool, update_descriptor_queue),
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quad_index_pass(device, scheduler, descriptor_pool, staging_pool, update_descriptor_queue) {}
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quad_index_pass(device, scheduler, descriptor_pool, staging_pool, update_descriptor_queue) {
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quad_array_index_buffer = std::make_shared<QuadArrayIndexBuffer>(device_, memory_allocator_,
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scheduler_, staging_pool_);
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quad_strip_index_buffer = std::make_shared<QuadStripIndexBuffer>(device_, memory_allocator_,
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scheduler_, staging_pool_);
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}
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StagingBufferRef BufferCacheRuntime::UploadStagingBuffer(size_t size) {
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return staging_pool.Request(size, MemoryUsage::Upload);
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@ -245,10 +422,11 @@ void BufferCacheRuntime::BindIndexBuffer(PrimitiveTopology topology, IndexFormat
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VkIndexType vk_index_type = MaxwellToVK::IndexFormat(index_format);
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VkDeviceSize vk_offset = offset;
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VkBuffer vk_buffer = buffer;
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if (topology == PrimitiveTopology::Quads) {
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if (topology == PrimitiveTopology::Quads || topology == PrimitiveTopology::QuadStrip) {
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vk_index_type = VK_INDEX_TYPE_UINT32;
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std::tie(vk_buffer, vk_offset) =
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quad_index_pass.Assemble(index_format, num_indices, base_vertex, buffer, offset);
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quad_index_pass.Assemble(index_format, num_indices, base_vertex, buffer, offset,
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topology == PrimitiveTopology::QuadStrip);
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} else if (vk_index_type == VK_INDEX_TYPE_UINT8_EXT && !device.IsExtIndexTypeUint8Supported()) {
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vk_index_type = VK_INDEX_TYPE_UINT16;
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std::tie(vk_buffer, vk_offset) = uint8_pass.Assemble(num_indices, buffer, offset);
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@ -263,7 +441,7 @@ void BufferCacheRuntime::BindIndexBuffer(PrimitiveTopology topology, IndexFormat
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});
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}
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void BufferCacheRuntime::BindQuadArrayIndexBuffer(u32 first, u32 count) {
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void BufferCacheRuntime::BindQuadIndexBuffer(PrimitiveTopology topology, u32 first, u32 count) {
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if (count == 0) {
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ReserveNullBuffer();
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scheduler.Record([this](vk::CommandBuffer cmdbuf) {
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@ -271,16 +449,14 @@ void BufferCacheRuntime::BindQuadArrayIndexBuffer(u32 first, u32 count) {
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});
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return;
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}
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ReserveQuadArrayLUT(first + count, true);
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// The LUT has the indices 0, 1, 2, and 3 copied as an array
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// To apply these 'first' offsets we can apply an offset based on the modulus.
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const VkIndexType index_type = quad_array_lut_index_type;
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const size_t sub_first_offset = static_cast<size_t>(first % 4) * (current_num_indices / 4);
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const size_t offset = (sub_first_offset + first / 4) * 6ULL * BytesPerIndex(index_type);
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scheduler.Record([buffer = *quad_array_lut, index_type, offset](vk::CommandBuffer cmdbuf) {
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cmdbuf.BindIndexBuffer(buffer, offset, index_type);
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});
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if (topology == PrimitiveTopology::Quads) {
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quad_array_index_buffer->UpdateBuffer(first + count);
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quad_array_index_buffer->BindBuffer(first);
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} else if (topology == PrimitiveTopology::QuadStrip) {
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quad_strip_index_buffer->UpdateBuffer(first + count);
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quad_strip_index_buffer->BindBuffer(first);
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}
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}
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void BufferCacheRuntime::BindVertexBuffer(u32 index, VkBuffer buffer, u32 offset, u32 size,
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@ -320,83 +496,6 @@ void BufferCacheRuntime::BindTransformFeedbackBuffer(u32 index, VkBuffer buffer,
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});
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}
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void BufferCacheRuntime::ReserveQuadArrayLUT(u32 num_indices, bool wait_for_idle) {
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if (num_indices <= current_num_indices) {
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return;
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}
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if (wait_for_idle) {
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scheduler.Finish();
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}
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current_num_indices = num_indices;
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quad_array_lut_index_type = IndexTypeFromNumElements(device, num_indices);
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const u32 num_quads = num_indices / 4;
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const u32 num_triangle_indices = num_quads * 6;
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const u32 num_first_offset_copies = 4;
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const size_t bytes_per_index = BytesPerIndex(quad_array_lut_index_type);
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const size_t size_bytes = num_triangle_indices * bytes_per_index * num_first_offset_copies;
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quad_array_lut = device.GetLogical().CreateBuffer(VkBufferCreateInfo{
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.sType = VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.size = size_bytes,
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.usage = VK_BUFFER_USAGE_INDEX_BUFFER_BIT | VK_BUFFER_USAGE_TRANSFER_DST_BIT,
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.sharingMode = VK_SHARING_MODE_EXCLUSIVE,
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.queueFamilyIndexCount = 0,
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.pQueueFamilyIndices = nullptr,
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});
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if (device.HasDebuggingToolAttached()) {
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quad_array_lut.SetObjectNameEXT("Quad LUT");
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}
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quad_array_lut_commit = memory_allocator.Commit(quad_array_lut, MemoryUsage::DeviceLocal);
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const StagingBufferRef staging = staging_pool.Request(size_bytes, MemoryUsage::Upload);
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u8* staging_data = staging.mapped_span.data();
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const size_t quad_size = bytes_per_index * 6;
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for (u32 first = 0; first < num_first_offset_copies; ++first) {
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for (u32 quad = 0; quad < num_quads; ++quad) {
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switch (quad_array_lut_index_type) {
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case VK_INDEX_TYPE_UINT8_EXT:
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std::memcpy(staging_data, MakeQuadIndices<u8>(quad, first).data(), quad_size);
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break;
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case VK_INDEX_TYPE_UINT16:
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std::memcpy(staging_data, MakeQuadIndices<u16>(quad, first).data(), quad_size);
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break;
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case VK_INDEX_TYPE_UINT32:
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std::memcpy(staging_data, MakeQuadIndices<u32>(quad, first).data(), quad_size);
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break;
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default:
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ASSERT(false);
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break;
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}
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staging_data += quad_size;
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}
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}
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scheduler.RequestOutsideRenderPassOperationContext();
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scheduler.Record([src_buffer = staging.buffer, src_offset = staging.offset,
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dst_buffer = *quad_array_lut, size_bytes](vk::CommandBuffer cmdbuf) {
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const VkBufferCopy copy{
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.srcOffset = src_offset,
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.dstOffset = 0,
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.size = size_bytes,
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};
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const VkBufferMemoryBarrier write_barrier{
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.sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER,
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.pNext = nullptr,
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.srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT,
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.dstAccessMask = VK_ACCESS_INDEX_READ_BIT,
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.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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.buffer = dst_buffer,
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.offset = 0,
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.size = size_bytes,
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};
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cmdbuf.CopyBuffer(src_buffer, dst_buffer, copy);
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cmdbuf.PipelineBarrier(VK_PIPELINE_STAGE_TRANSFER_BIT, VK_PIPELINE_STAGE_VERTEX_INPUT_BIT,
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0, write_barrier);
|
||||
});
|
||||
}
|
||||
|
||||
void BufferCacheRuntime::ReserveNullBuffer() {
|
||||
if (null_buffer) {
|
||||
return;
|
||||
|
@ -50,6 +50,9 @@ private:
|
||||
std::vector<BufferView> views;
|
||||
};
|
||||
|
||||
class QuadArrayIndexBuffer;
|
||||
class QuadStripIndexBuffer;
|
||||
|
||||
class BufferCacheRuntime {
|
||||
friend Buffer;
|
||||
|
||||
@ -86,7 +89,7 @@ public:
|
||||
void BindIndexBuffer(PrimitiveTopology topology, IndexFormat index_format, u32 num_indices,
|
||||
u32 base_vertex, VkBuffer buffer, u32 offset, u32 size);
|
||||
|
||||
void BindQuadArrayIndexBuffer(u32 first, u32 count);
|
||||
void BindQuadIndexBuffer(PrimitiveTopology topology, u32 first, u32 count);
|
||||
|
||||
void BindVertexBuffer(u32 index, VkBuffer buffer, u32 offset, u32 size, u32 stride);
|
||||
|
||||
@ -118,8 +121,6 @@ private:
|
||||
update_descriptor_queue.AddBuffer(buffer, offset, size);
|
||||
}
|
||||
|
||||
void ReserveQuadArrayLUT(u32 num_indices, bool wait_for_idle);
|
||||
|
||||
void ReserveNullBuffer();
|
||||
|
||||
const Device& device;
|
||||
@ -128,10 +129,8 @@ private:
|
||||
StagingBufferPool& staging_pool;
|
||||
UpdateDescriptorQueue& update_descriptor_queue;
|
||||
|
||||
vk::Buffer quad_array_lut;
|
||||
MemoryCommit quad_array_lut_commit;
|
||||
VkIndexType quad_array_lut_index_type{};
|
||||
u32 current_num_indices = 0;
|
||||
std::shared_ptr<QuadArrayIndexBuffer> quad_array_index_buffer;
|
||||
std::shared_ptr<QuadStripIndexBuffer> quad_strip_index_buffer;
|
||||
|
||||
vk::Buffer null_buffer;
|
||||
MemoryCommit null_buffer_commit;
|
||||
|
@ -245,7 +245,7 @@ QuadIndexedPass::QuadIndexedPass(const Device& device_, Scheduler& scheduler_,
|
||||
UpdateDescriptorQueue& update_descriptor_queue_)
|
||||
: ComputePass(device_, descriptor_pool_, INPUT_OUTPUT_DESCRIPTOR_SET_BINDINGS,
|
||||
INPUT_OUTPUT_DESCRIPTOR_UPDATE_TEMPLATE, INPUT_OUTPUT_BANK_INFO,
|
||||
COMPUTE_PUSH_CONSTANT_RANGE<sizeof(u32) * 2>, VULKAN_QUAD_INDEXED_COMP_SPV),
|
||||
COMPUTE_PUSH_CONSTANT_RANGE<sizeof(u32) * 3>, VULKAN_QUAD_INDEXED_COMP_SPV),
|
||||
scheduler{scheduler_}, staging_buffer_pool{staging_buffer_pool_},
|
||||
update_descriptor_queue{update_descriptor_queue_} {}
|
||||
|
||||
@ -253,7 +253,7 @@ QuadIndexedPass::~QuadIndexedPass() = default;
|
||||
|
||||
std::pair<VkBuffer, VkDeviceSize> QuadIndexedPass::Assemble(
|
||||
Tegra::Engines::Maxwell3D::Regs::IndexFormat index_format, u32 num_vertices, u32 base_vertex,
|
||||
VkBuffer src_buffer, u32 src_offset) {
|
||||
VkBuffer src_buffer, u32 src_offset, bool is_strip) {
|
||||
const u32 index_shift = [index_format] {
|
||||
switch (index_format) {
|
||||
case Tegra::Engines::Maxwell3D::Regs::IndexFormat::UnsignedByte:
|
||||
@ -267,7 +267,7 @@ std::pair<VkBuffer, VkDeviceSize> QuadIndexedPass::Assemble(
|
||||
return 2;
|
||||
}();
|
||||
const u32 input_size = num_vertices << index_shift;
|
||||
const u32 num_tri_vertices = (num_vertices / 4) * 6;
|
||||
const u32 num_tri_vertices = (is_strip ? (num_vertices - 2) / 2 : num_vertices / 4) * 6;
|
||||
|
||||
const std::size_t staging_size = num_tri_vertices * sizeof(u32);
|
||||
const auto staging = staging_buffer_pool.Request(staging_size, MemoryUsage::DeviceLocal);
|
||||
@ -278,8 +278,8 @@ std::pair<VkBuffer, VkDeviceSize> QuadIndexedPass::Assemble(
|
||||
const void* const descriptor_data{update_descriptor_queue.UpdateData()};
|
||||
|
||||
scheduler.RequestOutsideRenderPassOperationContext();
|
||||
scheduler.Record([this, descriptor_data, num_tri_vertices, base_vertex,
|
||||
index_shift](vk::CommandBuffer cmdbuf) {
|
||||
scheduler.Record([this, descriptor_data, num_tri_vertices, base_vertex, index_shift,
|
||||
is_strip](vk::CommandBuffer cmdbuf) {
|
||||
static constexpr u32 DISPATCH_SIZE = 1024;
|
||||
static constexpr VkMemoryBarrier WRITE_BARRIER{
|
||||
.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER,
|
||||
@ -287,7 +287,7 @@ std::pair<VkBuffer, VkDeviceSize> QuadIndexedPass::Assemble(
|
||||
.srcAccessMask = VK_ACCESS_SHADER_WRITE_BIT,
|
||||
.dstAccessMask = VK_ACCESS_INDEX_READ_BIT,
|
||||
};
|
||||
const std::array<u32, 2> push_constants{base_vertex, index_shift};
|
||||
const std::array<u32, 3> push_constants{base_vertex, index_shift, is_strip ? 1u : 0u};
|
||||
const VkDescriptorSet set = descriptor_allocator.Commit();
|
||||
device.GetLogical().UpdateDescriptorSet(set, *descriptor_template, descriptor_data);
|
||||
cmdbuf.BindPipeline(VK_PIPELINE_BIND_POINT_COMPUTE, *pipeline);
|
||||
|
@ -74,7 +74,7 @@ public:
|
||||
|
||||
std::pair<VkBuffer, VkDeviceSize> Assemble(
|
||||
Tegra::Engines::Maxwell3D::Regs::IndexFormat index_format, u32 num_vertices,
|
||||
u32 base_vertex, VkBuffer src_buffer, u32 src_offset);
|
||||
u32 base_vertex, VkBuffer src_buffer, u32 src_offset, bool is_strip);
|
||||
|
||||
private:
|
||||
Scheduler& scheduler;
|
||||
|
@ -138,12 +138,16 @@ DrawParams MakeDrawParams(const MaxwellDrawState& draw_state, u32 num_instances,
|
||||
.first_index = is_indexed ? draw_state.index_buffer.first : 0,
|
||||
.is_indexed = is_indexed,
|
||||
};
|
||||
// 6 triangle vertices per quad, base vertex is part of the index
|
||||
// See BindQuadIndexBuffer for more details
|
||||
if (draw_state.topology == Maxwell::PrimitiveTopology::Quads) {
|
||||
// 6 triangle vertices per quad, base vertex is part of the index
|
||||
// See BindQuadArrayIndexBuffer for more details
|
||||
params.num_vertices = (params.num_vertices / 4) * 6;
|
||||
params.base_vertex = 0;
|
||||
params.is_indexed = true;
|
||||
} else if (draw_state.topology == Maxwell::PrimitiveTopology::QuadStrip) {
|
||||
params.num_vertices = (params.num_vertices - 2) / 2 * 6;
|
||||
params.base_vertex = 0;
|
||||
params.is_indexed = true;
|
||||
}
|
||||
return params;
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user