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GPU: Store shader constbuffer bindings in the GPU state.
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66dae22790
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@ -43,6 +43,26 @@ void Maxwell3D::WriteReg(u32 method, u32 value) {
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ASSERT_MSG(regs.code_address.CodeAddress() == 0, "Unexpected CODE_ADDRESS register value.");
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ASSERT_MSG(regs.code_address.CodeAddress() == 0, "Unexpected CODE_ADDRESS register value.");
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break;
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break;
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}
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}
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case MAXWELL3D_REG_INDEX(cb_bind[0].raw_config): {
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ProcessCBBind(Regs::ShaderType::Vertex);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[1].raw_config): {
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ProcessCBBind(Regs::ShaderType::TesselationControl);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[2].raw_config): {
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ProcessCBBind(Regs::ShaderType::TesselationEval);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[3].raw_config): {
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ProcessCBBind(Regs::ShaderType::Geometry);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[4].raw_config): {
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ProcessCBBind(Regs::ShaderType::Fragment);
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break;
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}
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case MAXWELL3D_REG_INDEX(draw.vertex_end_gl): {
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case MAXWELL3D_REG_INDEX(draw.vertex_end_gl): {
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DrawArrays();
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DrawArrays();
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break;
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break;
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@ -95,11 +115,10 @@ void Maxwell3D::SetShader(const std::vector<u32>& parameters) {
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auto shader_type = static_cast<Regs::ShaderType>(parameters[3]);
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auto shader_type = static_cast<Regs::ShaderType>(parameters[3]);
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GPUVAddr cb_address = parameters[4] << 8;
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GPUVAddr cb_address = parameters[4] << 8;
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auto& shader = state.shaders[static_cast<size_t>(shader_program)];
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auto& shader = state.shader_programs[static_cast<size_t>(shader_program)];
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shader.program = shader_program;
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shader.program = shader_program;
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shader.type = shader_type;
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shader.type = shader_type;
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shader.address = address;
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shader.address = address;
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shader.cb_address = cb_address;
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// Perform the same operations as the real macro code.
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// Perform the same operations as the real macro code.
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// TODO(Subv): Early exit if register 0xD1C + shader_program contains the same as params[1].
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// TODO(Subv): Early exit if register 0xD1C + shader_program contains the same as params[1].
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@ -118,6 +137,21 @@ void Maxwell3D::SetShader(const std::vector<u32>& parameters) {
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// shader. It's likely that these are the constants for the shader.
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// shader. It's likely that these are the constants for the shader.
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regs.cb_bind[static_cast<size_t>(shader_type)].valid.Assign(1);
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regs.cb_bind[static_cast<size_t>(shader_type)].valid.Assign(1);
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regs.cb_bind[static_cast<size_t>(shader_type)].index.Assign(1);
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regs.cb_bind[static_cast<size_t>(shader_type)].index.Assign(1);
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ProcessCBBind(shader_type);
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}
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void Maxwell3D::ProcessCBBind(Regs::ShaderType stage) {
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// Bind the buffer currently in CB_ADDRESS to the specified index in the desired shader stage.
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auto& shader = state.shader_stages[static_cast<size_t>(stage)];
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auto& bind_data = regs.cb_bind[static_cast<size_t>(stage)];
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auto& buffer = shader.const_buffers[bind_data.index];
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buffer.enabled = bind_data.valid.Value() != 0;
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buffer.index = bind_data.index;
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buffer.address = regs.const_buffer.BufferAddress();
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buffer.size = regs.const_buffer.cb_size;
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}
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}
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} // namespace Engines
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} // namespace Engines
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@ -39,6 +39,8 @@ public:
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static constexpr size_t NumVertexArrays = 32;
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static constexpr size_t NumVertexArrays = 32;
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static constexpr size_t MaxShaderProgram = 6;
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static constexpr size_t MaxShaderProgram = 6;
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static constexpr size_t MaxShaderType = 5;
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static constexpr size_t MaxShaderType = 5;
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// Maximum number of const buffers per shader stage.
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static constexpr size_t MaxConstBuffers = 16;
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enum class QueryMode : u32 {
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enum class QueryMode : u32 {
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Write = 0,
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Write = 0,
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@ -146,12 +148,18 @@ public:
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u32 cb_address_low;
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u32 cb_address_low;
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u32 cb_pos;
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u32 cb_pos;
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u32 cb_data[NumCBData];
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u32 cb_data[NumCBData];
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GPUVAddr BufferAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(cb_address_high) << 32) | cb_address_low);
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}
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} const_buffer;
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} const_buffer;
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INSERT_PADDING_WORDS(0x10);
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INSERT_PADDING_WORDS(0x10);
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struct {
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struct {
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union {
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union {
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u32 raw_config;
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BitField<0, 1, u32> valid;
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BitField<0, 1, u32> valid;
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BitField<4, 5, u32> index;
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BitField<4, 5, u32> index;
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};
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};
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@ -167,14 +175,25 @@ public:
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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struct State {
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struct State {
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struct ShaderInfo {
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struct ConstBufferInfo {
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GPUVAddr address;
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u32 index;
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u32 size;
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bool enabled;
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};
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struct ShaderProgramInfo {
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Regs::ShaderType type;
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Regs::ShaderType type;
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Regs::ShaderProgram program;
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Regs::ShaderProgram program;
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GPUVAddr address;
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GPUVAddr address;
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GPUVAddr cb_address;
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};
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};
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std::array<ShaderInfo, Regs::MaxShaderProgram> shaders;
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struct ShaderStageInfo {
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std::array<ConstBufferInfo, Regs::MaxConstBuffers> const_buffers;
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};
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std::array<ShaderStageInfo, Regs::MaxShaderType> shader_stages;
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std::array<ShaderProgramInfo, Regs::MaxShaderProgram> shader_programs;
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};
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};
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State state{};
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State state{};
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@ -185,6 +204,9 @@ private:
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/// Handles a write to the QUERY_GET register.
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/// Handles a write to the QUERY_GET register.
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void ProcessQueryGet();
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void ProcessQueryGet();
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/// Handles a write to the CB_BIND register.
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void ProcessCBBind(Regs::ShaderType stage);
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/// Handles a write to the VERTEX_END_GL register, triggering a draw.
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/// Handles a write to the VERTEX_END_GL register, triggering a draw.
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void DrawArrays();
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void DrawArrays();
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