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Merge pull request #935 from lioncash/smlaw
arm_dyncom_interpreter: Simplify assignment in SMLAW
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@ -5695,7 +5695,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF);
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const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16);
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RD = (result & (0xFFFFFFFFFFFFFFFFLL >> 15)) >> 16;
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RD = BITS(result, 16, 47);
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if ((result >> 16) != (s32)RD)
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cpu->Cpsr |= (1 << 27);
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