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synced 2024-08-20 16:33:22 +02:00
vk_pipeline_cache: Unify pipeline cache keys into a single operation
This allows us to call Common::CityHash and std::memcmp only once for GraphicsPipelineCacheKey. While we are at it, do the same for compute.
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f665c92114
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@ -140,6 +140,12 @@ void FixedPipelineState::BlendingAttachment::Fill(const Maxwell& regs, std::size
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enable.Assign(1);
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}
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void FixedPipelineState::Fill(const Maxwell& regs) {
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rasterizer.Fill(regs);
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depth_stencil.Fill(regs);
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color_blending.Fill(regs);
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}
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std::size_t FixedPipelineState::Hash() const noexcept {
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const u64 hash = Common::CityHash64(reinterpret_cast<const char*>(this), sizeof *this);
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return static_cast<std::size_t>(hash);
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@ -149,15 +155,6 @@ bool FixedPipelineState::operator==(const FixedPipelineState& rhs) const noexcep
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return std::memcmp(this, &rhs, sizeof *this) == 0;
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}
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FixedPipelineState GetFixedPipelineState(const Maxwell& regs) {
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FixedPipelineState fixed_state;
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fixed_state.rasterizer.Fill(regs);
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fixed_state.depth_stencil.Fill(regs);
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fixed_state.color_blending.Fill(regs);
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fixed_state.padding = {};
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return fixed_state;
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}
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u32 FixedPipelineState::PackComparisonOp(Maxwell::ComparisonOp op) noexcept {
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// OpenGL enums go from 0x200 to 0x207 and the others from 1 to 8
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// If we substract 0x200 to OpenGL enums and 1 to the others we get a 0-7 range.
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@ -17,7 +17,7 @@ namespace Vulkan {
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using Maxwell = Tegra::Engines::Maxwell3D::Regs;
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struct alignas(32) FixedPipelineState {
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struct FixedPipelineState {
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static u32 PackComparisonOp(Maxwell::ComparisonOp op) noexcept;
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static Maxwell::ComparisonOp UnpackComparisonOp(u32 packed) noexcept;
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@ -237,7 +237,8 @@ struct alignas(32) FixedPipelineState {
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Rasterizer rasterizer;
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DepthStencil depth_stencil;
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ColorBlending color_blending;
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std::array<u8, 20> padding;
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void Fill(const Maxwell& regs);
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std::size_t Hash() const noexcept;
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@ -250,9 +251,6 @@ struct alignas(32) FixedPipelineState {
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static_assert(std::has_unique_object_representations_v<FixedPipelineState>);
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static_assert(std::is_trivially_copyable_v<FixedPipelineState>);
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static_assert(std::is_trivially_constructible_v<FixedPipelineState>);
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static_assert(sizeof(FixedPipelineState) % 32 == 0, "Size is not aligned");
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FixedPipelineState GetFixedPipelineState(const Maxwell& regs);
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} // namespace Vulkan
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@ -161,6 +161,24 @@ u32 FillDescriptorLayout(const ShaderEntries& entries,
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} // Anonymous namespace
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std::size_t GraphicsPipelineCacheKey::Hash() const noexcept {
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const u64 hash = Common::CityHash64(reinterpret_cast<const char*>(this), sizeof *this);
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return static_cast<std::size_t>(hash);
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}
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bool GraphicsPipelineCacheKey::operator==(const GraphicsPipelineCacheKey& rhs) const noexcept {
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return std::memcmp(&rhs, this, sizeof *this) == 0;
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}
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std::size_t ComputePipelineCacheKey::Hash() const noexcept {
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const u64 hash = Common::CityHash64(reinterpret_cast<const char*>(this), sizeof *this);
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return static_cast<std::size_t>(hash);
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}
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bool ComputePipelineCacheKey::operator==(const ComputePipelineCacheKey& rhs) const noexcept {
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return std::memcmp(&rhs, this, sizeof *this) == 0;
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}
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CachedShader::CachedShader(Core::System& system, Tegra::Engines::ShaderType stage,
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GPUVAddr gpu_addr, VAddr cpu_addr, ProgramCode program_code,
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u32 main_offset)
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@ -7,7 +7,6 @@
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#include <array>
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#include <cstddef>
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#include <memory>
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#include <tuple>
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#include <type_traits>
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#include <unordered_map>
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#include <utility>
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@ -51,42 +50,38 @@ using ProgramCode = std::vector<u64>;
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struct GraphicsPipelineCacheKey {
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FixedPipelineState fixed_state;
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std::array<GPUVAddr, Maxwell::MaxShaderProgram> shaders;
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RenderPassParams renderpass_params;
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std::array<GPUVAddr, Maxwell::MaxShaderProgram> shaders;
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u64 padding; // This is necessary for unique object representations
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std::size_t Hash() const noexcept {
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std::size_t hash = fixed_state.Hash();
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for (const auto& shader : shaders) {
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boost::hash_combine(hash, shader);
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}
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boost::hash_combine(hash, renderpass_params.Hash());
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return hash;
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}
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std::size_t Hash() const noexcept;
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bool operator==(const GraphicsPipelineCacheKey& rhs) const noexcept {
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return std::tie(fixed_state, shaders, renderpass_params) ==
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std::tie(rhs.fixed_state, rhs.shaders, rhs.renderpass_params);
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bool operator==(const GraphicsPipelineCacheKey& rhs) const noexcept;
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bool operator!=(const GraphicsPipelineCacheKey& rhs) const noexcept {
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return !operator==(rhs);
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}
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};
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static_assert(std::has_unique_object_representations_v<GraphicsPipelineCacheKey>);
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static_assert(std::is_trivially_copyable_v<GraphicsPipelineCacheKey>);
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static_assert(std::is_trivially_constructible_v<GraphicsPipelineCacheKey>);
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struct ComputePipelineCacheKey {
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GPUVAddr shader{};
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u32 shared_memory_size{};
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std::array<u32, 3> workgroup_size{};
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GPUVAddr shader;
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u32 shared_memory_size;
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std::array<u32, 3> workgroup_size;
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std::size_t Hash() const noexcept {
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return static_cast<std::size_t>(shader) ^
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((static_cast<std::size_t>(shared_memory_size) >> 7) << 40) ^
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static_cast<std::size_t>(workgroup_size[0]) ^
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(static_cast<std::size_t>(workgroup_size[1]) << 16) ^
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(static_cast<std::size_t>(workgroup_size[2]) << 24);
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}
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std::size_t Hash() const noexcept;
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bool operator==(const ComputePipelineCacheKey& rhs) const noexcept {
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return std::tie(shader, shared_memory_size, workgroup_size) ==
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std::tie(rhs.shader, rhs.shared_memory_size, rhs.workgroup_size);
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bool operator==(const ComputePipelineCacheKey& rhs) const noexcept;
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bool operator!=(const ComputePipelineCacheKey& rhs) const noexcept {
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return !operator==(rhs);
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}
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};
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static_assert(std::has_unique_object_representations_v<ComputePipelineCacheKey>);
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static_assert(std::is_trivially_copyable_v<ComputePipelineCacheKey>);
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static_assert(std::is_trivially_constructible_v<ComputePipelineCacheKey>);
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} // namespace Vulkan
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@ -316,7 +316,8 @@ void RasterizerVulkan::Draw(bool is_indexed, bool is_instanced) {
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query_cache.UpdateCounters();
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const auto& gpu = system.GPU().Maxwell3D();
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GraphicsPipelineCacheKey key{GetFixedPipelineState(gpu.regs)};
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GraphicsPipelineCacheKey key;
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key.fixed_state.Fill(gpu.regs);
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buffer_cache.Map(CalculateGraphicsStreamBufferSize(is_indexed));
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@ -334,10 +335,11 @@ void RasterizerVulkan::Draw(bool is_indexed, bool is_instanced) {
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buffer_cache.Unmap();
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const auto texceptions = UpdateAttachments();
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const Texceptions texceptions = UpdateAttachments();
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SetupImageTransitions(texceptions, color_attachments, zeta_attachment);
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key.renderpass_params = GetRenderPassParams(texceptions);
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key.padding = 0;
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auto& pipeline = pipeline_cache.GetGraphicsPipeline(key);
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scheduler.BindGraphicsPipeline(pipeline.GetHandle());
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@ -453,10 +455,12 @@ void RasterizerVulkan::DispatchCompute(GPUVAddr code_addr) {
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query_cache.UpdateCounters();
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const auto& launch_desc = system.GPU().KeplerCompute().launch_description;
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const ComputePipelineCacheKey key{
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code_addr,
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launch_desc.shared_alloc,
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{launch_desc.block_dim_x, launch_desc.block_dim_y, launch_desc.block_dim_z}};
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ComputePipelineCacheKey key;
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key.shader = code_addr;
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key.shared_memory_size = launch_desc.shared_alloc;
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key.workgroup_size = {launch_desc.block_dim_x, launch_desc.block_dim_y,
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launch_desc.block_dim_z};
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auto& pipeline = pipeline_cache.GetComputePipeline(key);
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// Compute dispatches can't be executed inside a renderpass
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