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shader: Implement SHF
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5465cb1561
commit
924f0a9149
@ -78,6 +78,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/integer_add_three_input.cpp
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frontend/maxwell/translate/impl/integer_add_three_input.cpp
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frontend/maxwell/translate/impl/integer_compare.cpp
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frontend/maxwell/translate/impl/integer_compare.cpp
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frontend/maxwell/translate/impl/integer_compare_and_set.cpp
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frontend/maxwell/translate/impl/integer_compare_and_set.cpp
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frontend/maxwell/translate/impl/integer_funnel_shift.cpp
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frontend/maxwell/translate/impl/integer_minimum_maximum.cpp
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frontend/maxwell/translate/impl/integer_minimum_maximum.cpp
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frontend/maxwell/translate/impl/integer_popcount.cpp
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frontend/maxwell/translate/impl/integer_popcount.cpp
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frontend/maxwell/translate/impl/integer_scaled_add.cpp
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frontend/maxwell/translate/impl/integer_scaled_add.cpp
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@ -232,9 +232,11 @@ Id EmitINeg32(EmitContext& ctx, Id value);
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Id EmitINeg64(EmitContext& ctx, Id value);
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Id EmitINeg64(EmitContext& ctx, Id value);
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Id EmitIAbs32(EmitContext& ctx, Id value);
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Id EmitIAbs32(EmitContext& ctx, Id value);
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Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
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Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
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Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b);
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Id EmitShiftLeftLogical64(EmitContext& ctx, Id base, Id shift);
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Id EmitShiftRightLogical64(EmitContext& ctx, Id a, Id b);
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Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift);
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Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b);
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Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift);
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Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift);
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Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift);
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Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b);
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Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b);
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Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b);
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Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b);
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Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b);
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Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b);
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@ -74,16 +74,24 @@ Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
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return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
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}
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}
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Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b) {
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Id EmitShiftLeftLogical64(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftRightLogical(ctx.U32[1], a, b);
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return ctx.OpShiftLeftLogical(ctx.U64, base, shift);
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}
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}
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Id EmitShiftRightLogical64(EmitContext& ctx, Id a, Id b) {
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Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftRightLogical(ctx.U64, a, b);
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return ctx.OpShiftRightLogical(ctx.U32[1], base, shift);
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}
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}
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Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b) {
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Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftRightArithmetic(ctx.U32[1], a, b);
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return ctx.OpShiftRightLogical(ctx.U64, base, shift);
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}
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Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftRightArithmetic(ctx.U32[1], base, shift);
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}
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Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift) {
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return ctx.OpShiftRightArithmetic(ctx.U64, base, shift);
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}
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}
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Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) {
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Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) {
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@ -813,8 +813,15 @@ U32 IREmitter::IAbs(const U32& value) {
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return Inst<U32>(Opcode::IAbs32, value);
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return Inst<U32>(Opcode::IAbs32, value);
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}
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}
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U32 IREmitter::ShiftLeftLogical(const U32& base, const U32& shift) {
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U32U64 IREmitter::ShiftLeftLogical(const U32U64& base, const U32& shift) {
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return Inst<U32>(Opcode::ShiftLeftLogical32, base, shift);
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switch (base.Type()) {
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case Type::U32:
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return Inst<U32>(Opcode::ShiftLeftLogical32, base, shift);
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case Type::U64:
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return Inst<U64>(Opcode::ShiftLeftLogical64, base, shift);
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default:
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ThrowInvalidType(base.Type());
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}
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}
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}
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U32U64 IREmitter::ShiftRightLogical(const U32U64& base, const U32& shift) {
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U32U64 IREmitter::ShiftRightLogical(const U32U64& base, const U32& shift) {
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@ -828,8 +835,15 @@ U32U64 IREmitter::ShiftRightLogical(const U32U64& base, const U32& shift) {
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}
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}
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}
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}
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U32 IREmitter::ShiftRightArithmetic(const U32& base, const U32& shift) {
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U32U64 IREmitter::ShiftRightArithmetic(const U32U64& base, const U32& shift) {
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return Inst<U32>(Opcode::ShiftRightArithmetic32, base, shift);
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switch (base.Type()) {
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case Type::U32:
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return Inst<U32>(Opcode::ShiftRightArithmetic32, base, shift);
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case Type::U64:
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return Inst<U64>(Opcode::ShiftRightArithmetic64, base, shift);
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default:
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ThrowInvalidType(base.Type());
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}
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}
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}
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U32 IREmitter::BitwiseAnd(const U32& a, const U32& b) {
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U32 IREmitter::BitwiseAnd(const U32& a, const U32& b) {
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@ -150,9 +150,9 @@ public:
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[[nodiscard]] U32 IMul(const U32& a, const U32& b);
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[[nodiscard]] U32 IMul(const U32& a, const U32& b);
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[[nodiscard]] U32U64 INeg(const U32U64& value);
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[[nodiscard]] U32U64 INeg(const U32U64& value);
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[[nodiscard]] U32 IAbs(const U32& value);
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[[nodiscard]] U32 IAbs(const U32& value);
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[[nodiscard]] U32 ShiftLeftLogical(const U32& base, const U32& shift);
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[[nodiscard]] U32U64 ShiftLeftLogical(const U32U64& base, const U32& shift);
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[[nodiscard]] U32U64 ShiftRightLogical(const U32U64& base, const U32& shift);
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[[nodiscard]] U32U64 ShiftRightLogical(const U32U64& base, const U32& shift);
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[[nodiscard]] U32 ShiftRightArithmetic(const U32& base, const U32& shift);
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[[nodiscard]] U32U64 ShiftRightArithmetic(const U32U64& base, const U32& shift);
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[[nodiscard]] U32 BitwiseAnd(const U32& a, const U32& b);
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[[nodiscard]] U32 BitwiseAnd(const U32& a, const U32& b);
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[[nodiscard]] U32 BitwiseOr(const U32& a, const U32& b);
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[[nodiscard]] U32 BitwiseOr(const U32& a, const U32& b);
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[[nodiscard]] U32 BitwiseXor(const U32& a, const U32& b);
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[[nodiscard]] U32 BitwiseXor(const U32& a, const U32& b);
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@ -236,9 +236,11 @@ OPCODE(INeg32, U32, U32,
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OPCODE(INeg64, U64, U64, )
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OPCODE(INeg64, U64, U64, )
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OPCODE(IAbs32, U32, U32, )
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OPCODE(IAbs32, U32, U32, )
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OPCODE(ShiftLeftLogical32, U32, U32, U32, )
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OPCODE(ShiftLeftLogical32, U32, U32, U32, )
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OPCODE(ShiftLeftLogical64, U64, U64, U32, )
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OPCODE(ShiftRightLogical32, U32, U32, U32, )
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OPCODE(ShiftRightLogical32, U32, U32, U32, )
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OPCODE(ShiftRightLogical64, U64, U64, U32, )
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OPCODE(ShiftRightLogical64, U64, U64, U32, )
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OPCODE(ShiftRightArithmetic32, U32, U32, U32, )
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OPCODE(ShiftRightArithmetic32, U32, U32, U32, )
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OPCODE(ShiftRightArithmetic64, U64, U64, U32, )
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OPCODE(BitwiseAnd32, U32, U32, U32, )
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OPCODE(BitwiseAnd32, U32, U32, U32, )
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OPCODE(BitwiseOr32, U32, U32, U32, )
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OPCODE(BitwiseOr32, U32, U32, U32, )
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OPCODE(BitwiseXor32, U32, U32, U32, )
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OPCODE(BitwiseXor32, U32, U32, U32, )
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@ -0,0 +1,77 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class MaxShift : u64 {
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U32,
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Undefined,
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U64,
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S64,
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};
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IR::U64 PackedShift(IR::IREmitter& ir, const IR::U64& packed_int, const IR::U32& safe_shift,
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bool right_shift, bool is_signed) {
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if (!right_shift) {
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return ir.ShiftLeftLogical(packed_int, safe_shift);
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}
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if (is_signed) {
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return ir.ShiftRightArithmetic(packed_int, safe_shift);
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}
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return ir.ShiftRightLogical(packed_int, safe_shift);
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}
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void SHF(TranslatorVisitor& v, u64 insn, const IR::U32& shift, const IR::U32& high_bits,
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bool right_shift) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<0, 8, IR::Reg> lo_bits_reg;
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BitField<37, 2, MaxShift> max_shift;
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BitField<48, 2, u64> x_mode;
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BitField<50, 1, u64> wrap;
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} const shf{insn};
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if (shf.x_mode != 0) {
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throw NotImplementedException("SHF X Mode");
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}
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if (shf.max_shift == MaxShift::Undefined) {
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throw NotImplementedException("SHF Use of undefined MaxShift value");
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}
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const IR::U32 low_bits{v.X(shf.lo_bits_reg)};
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const IR::U64 packed_int{v.ir.PackUint2x32(v.ir.CompositeConstruct(low_bits, high_bits))};
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const IR::U32 max_shift{shf.max_shift == MaxShift::U32 ? v.ir.Imm32(32) : v.ir.Imm32(63)};
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const IR::U32 safe_shift{shf.wrap != 0
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? v.ir.BitwiseAnd(shift, v.ir.ISub(max_shift, v.ir.Imm32(1)))
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: v.ir.UMin(shift, max_shift)};
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const bool is_signed{shf.max_shift == MaxShift::S64};
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const IR::U64 shifted_value{PackedShift(v.ir, packed_int, safe_shift, right_shift, is_signed)};
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const IR::Value unpacked_value{v.ir.UnpackUint2x32(shifted_value)};
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const IR::U32 result{v.ir.CompositeExtract(unpacked_value, right_shift ? 0 : 1)};
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v.X(shf.dest_reg, result);
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}
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} // Anonymous namespace
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void TranslatorVisitor::SHF_l_reg(u64 insn) {
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SHF(*this, insn, GetReg20(insn), GetReg39(insn), false);
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}
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void TranslatorVisitor::SHF_l_imm(u64 insn) {
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SHF(*this, insn, GetImm20(insn), GetReg39(insn), false);
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}
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void TranslatorVisitor::SHF_r_reg(u64 insn) {
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SHF(*this, insn, GetReg20(insn), GetReg39(insn), true);
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}
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void TranslatorVisitor::SHF_r_imm(u64 insn) {
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SHF(*this, insn, GetImm20(insn), GetReg39(insn), true);
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}
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} // namespace Shader::Maxwell
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@ -553,22 +553,6 @@ void TranslatorVisitor::SETLMEMBASE(u64) {
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ThrowNotImplemented(Opcode::SETLMEMBASE);
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ThrowNotImplemented(Opcode::SETLMEMBASE);
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}
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}
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void TranslatorVisitor::SHF_l_reg(u64) {
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ThrowNotImplemented(Opcode::SHF_l_reg);
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}
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void TranslatorVisitor::SHF_l_imm(u64) {
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ThrowNotImplemented(Opcode::SHF_l_imm);
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}
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void TranslatorVisitor::SHF_r_reg(u64) {
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ThrowNotImplemented(Opcode::SHF_r_reg);
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}
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void TranslatorVisitor::SHF_r_imm(u64) {
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ThrowNotImplemented(Opcode::SHF_r_imm);
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}
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void TranslatorVisitor::SHFL(u64) {
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void TranslatorVisitor::SHFL(u64) {
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ThrowNotImplemented(Opcode::SHFL);
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ThrowNotImplemented(Opcode::SHFL);
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}
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}
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