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Merge pull request #2856 from wwylele/shader-share
pica: upload shared shader code & swizzle to both unit
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commit
93ab46e500
@ -119,27 +119,6 @@ static void WriteUniformFloatReg(ShaderRegs& config, Shader::ShaderSetup& setup,
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}
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}
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static void WriteProgramCode(ShaderRegs& config, Shader::ShaderSetup& setup,
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unsigned max_program_code_length, u32 value) {
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if (config.program.offset >= max_program_code_length) {
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LOG_ERROR(HW_GPU, "Invalid %s program offset %d", GetShaderSetupTypeName(setup),
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(int)config.program.offset);
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} else {
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setup.program_code[config.program.offset] = value;
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config.program.offset++;
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}
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}
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static void WriteSwizzlePatterns(ShaderRegs& config, Shader::ShaderSetup& setup, u32 value) {
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if (config.swizzle_patterns.offset >= setup.swizzle_data.size()) {
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LOG_ERROR(HW_GPU, "Invalid %s swizzle pattern offset %d", GetShaderSetupTypeName(setup),
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(int)config.swizzle_patterns.offset);
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} else {
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setup.swizzle_data[config.swizzle_patterns.offset] = value;
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config.swizzle_patterns.offset++;
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}
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}
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static void WritePicaReg(u32 id, u32 value, u32 mask) {
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auto& regs = g_state.regs;
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@ -458,7 +437,13 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[5], 0x2a1):
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case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[6], 0x2a2):
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case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[7], 0x2a3): {
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WriteProgramCode(g_state.regs.gs, g_state.gs, 4096, value);
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u32& offset = g_state.regs.gs.program.offset;
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if (offset >= 4096) {
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LOG_ERROR(HW_GPU, "Invalid GS program offset %u", offset);
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} else {
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g_state.gs.program_code[offset] = value;
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offset++;
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}
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break;
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}
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@ -470,11 +455,18 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[5], 0x2ab):
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case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[6], 0x2ac):
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case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[7], 0x2ad): {
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WriteSwizzlePatterns(g_state.regs.gs, g_state.gs, value);
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u32& offset = g_state.regs.gs.swizzle_patterns.offset;
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if (offset >= g_state.gs.swizzle_data.size()) {
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LOG_ERROR(HW_GPU, "Invalid GS swizzle pattern offset %u", offset);
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} else {
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g_state.gs.swizzle_data[offset] = value;
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offset++;
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}
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break;
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}
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case PICA_REG_INDEX(vs.bool_uniforms):
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// TODO (wwylele): does regs.pipeline.gs_unit_exclusive_configuration affect this?
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WriteUniformBoolReg(g_state.vs, g_state.regs.vs.bool_uniforms.Value());
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break;
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@ -482,6 +474,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[1], 0x2b2):
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case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[2], 0x2b3):
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case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[3], 0x2b4): {
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// TODO (wwylele): does regs.pipeline.gs_unit_exclusive_configuration affect this?
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unsigned index = (id - PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1));
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auto values = regs.vs.int_uniforms[index];
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WriteUniformIntReg(g_state.vs, index,
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@ -497,6 +490,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[5], 0x2c6):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[6], 0x2c7):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[7], 0x2c8): {
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// TODO (wwylele): does regs.pipeline.gs_unit_exclusive_configuration affect this?
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WriteUniformFloatReg(g_state.regs.vs, g_state.vs, vs_float_regs_counter,
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vs_uniform_write_buffer, value);
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break;
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@ -510,7 +504,16 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[5], 0x2d1):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[6], 0x2d2):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[7], 0x2d3): {
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WriteProgramCode(g_state.regs.vs, g_state.vs, 512, value);
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u32& offset = g_state.regs.vs.program.offset;
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if (offset >= 512) {
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LOG_ERROR(HW_GPU, "Invalid VS program offset %u", offset);
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} else {
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g_state.vs.program_code[offset] = value;
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if (!g_state.regs.pipeline.gs_unit_exclusive_configuration) {
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g_state.gs.program_code[offset] = value;
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}
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offset++;
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}
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break;
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}
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@ -522,7 +525,16 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[5], 0x2db):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[6], 0x2dc):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[7], 0x2dd): {
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WriteSwizzlePatterns(g_state.regs.vs, g_state.vs, value);
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u32& offset = g_state.regs.vs.swizzle_patterns.offset;
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if (offset >= g_state.vs.swizzle_data.size()) {
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LOG_ERROR(HW_GPU, "Invalid VS swizzle pattern offset %u", offset);
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} else {
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g_state.vs.swizzle_data[offset] = value;
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if (!g_state.regs.pipeline.gs_unit_exclusive_configuration) {
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g_state.gs.swizzle_data[offset] = value;
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}
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offset++;
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}
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break;
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}
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@ -202,7 +202,14 @@ struct PipelineRegs {
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/// Number of input attributes to the vertex shader minus 1
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BitField<0, 4, u32> max_input_attrib_index;
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INSERT_PADDING_WORDS(2);
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INSERT_PADDING_WORDS(1);
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// The shader unit 3, which can be used for both vertex and geometry shader, gets its
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// configuration depending on this register. If this is not set, unit 3 will share some
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// configuration with other units. It is known that program code and swizzle pattern uploaded
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// via regs.vs will be also uploaded to unit 3 if this is not set. Although very likely, it is
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// still unclear whether uniforms and other configuration can be also shared.
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BitField<0, 1, u32> gs_unit_exclusive_configuration;
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enum class GPUMode : u32 {
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Drawing = 0,
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