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shader: Add integer division opcodes
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43aa695a04
commit
95761cc6a7
@ -304,6 +304,8 @@ void EmitIAdd64(EmitContext& ctx, IR::Inst& inst, Register a, Register b);
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void EmitISub32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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void EmitISub64(EmitContext& ctx, IR::Inst& inst, Register a, Register b);
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void EmitIMul32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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void EmitSDiv32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b);
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void EmitUDiv32(EmitContext& ctx, IR::Inst& inst, ScalarU32 a, ScalarU32 b);
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void EmitINeg32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
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void EmitINeg64(EmitContext& ctx, IR::Inst& inst, Register value);
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void EmitIAbs32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value);
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@ -90,6 +90,14 @@ void EmitIMul32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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ctx.Add("MUL.S {}.x,{},{};", inst, a, b);
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}
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void EmitSDiv32(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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ctx.Add("DIV.S {}.x,{},{};", inst, a, b);
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}
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void EmitUDiv32(EmitContext& ctx, IR::Inst& inst, ScalarU32 a, ScalarU32 b) {
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ctx.Add("DIV.U {}.x,{},{};", inst, a, b);
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}
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void EmitINeg32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) {
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if (value.type != Type::Register && static_cast<s32>(value.imm_u32) < 0) {
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ctx.Add("MOV.S {},{};", inst, -static_cast<s32>(value.imm_u32));
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@ -363,6 +363,8 @@ void EmitIAdd64(EmitContext& ctx, IR::Inst& inst, std::string_view a, std::strin
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void EmitISub32(EmitContext& ctx, IR::Inst& inst, std::string_view a, std::string_view b);
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void EmitISub64(EmitContext& ctx, IR::Inst& inst, std::string_view a, std::string_view b);
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void EmitIMul32(EmitContext& ctx, IR::Inst& inst, std::string_view a, std::string_view b);
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void EmitSDiv32(EmitContext& ctx, IR::Inst& inst, std::string_view a, std::string_view b);
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void EmitUDiv32(EmitContext& ctx, IR::Inst& inst, std::string_view a, std::string_view b);
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void EmitINeg32(EmitContext& ctx, IR::Inst& inst, std::string_view value);
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void EmitINeg64(EmitContext& ctx, IR::Inst& inst, std::string_view value);
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void EmitIAbs32(EmitContext& ctx, IR::Inst& inst, std::string_view value);
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@ -78,6 +78,14 @@ void EmitIMul32(EmitContext& ctx, IR::Inst& inst, std::string_view a, std::strin
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ctx.AddU32("{}=uint({}*{});", inst, a, b);
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}
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void EmitSDiv32(EmitContext& ctx, IR::Inst& inst, std::string_view a, std::string_view b) {
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ctx.AddU32("{}=uint(int({})/int({}));", inst, a, b);
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}
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void EmitUDiv32(EmitContext& ctx, IR::Inst& inst, std::string_view a, std::string_view b) {
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ctx.AddU32("{}={}/{};", inst, a, b);
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}
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void EmitINeg32(EmitContext& ctx, IR::Inst& inst, std::string_view value) {
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ctx.AddU32("{}=uint(-({}));", inst, value);
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}
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@ -284,6 +284,8 @@ Id EmitIAdd64(EmitContext& ctx, Id a, Id b);
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Id EmitISub32(EmitContext& ctx, Id a, Id b);
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Id EmitISub64(EmitContext& ctx, Id a, Id b);
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Id EmitIMul32(EmitContext& ctx, Id a, Id b);
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Id EmitSDiv32(EmitContext& ctx, Id a, Id b);
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Id EmitUDiv32(EmitContext& ctx, Id a, Id b);
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Id EmitINeg32(EmitContext& ctx, Id value);
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Id EmitINeg64(EmitContext& ctx, Id value);
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Id EmitIAbs32(EmitContext& ctx, Id value);
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@ -72,6 +72,14 @@ Id EmitIMul32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpIMul(ctx.U32[1], a, b);
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}
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Id EmitSDiv32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpSDiv(ctx.U32[1], a, b);
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}
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Id EmitUDiv32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpUDiv(ctx.U32[1], a, b);
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}
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Id EmitINeg32(EmitContext& ctx, Id value) {
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return ctx.OpSNegate(ctx.U32[1], value);
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}
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@ -1145,6 +1145,10 @@ U32 IREmitter::IMul(const U32& a, const U32& b) {
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return Inst<U32>(Opcode::IMul32, a, b);
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}
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U32 IREmitter::IDiv(const U32& a, const U32& b, bool is_signed) {
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return Inst<U32>(is_signed ? Opcode::SDiv32 : Opcode::UDiv32, a, b);
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}
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U32U64 IREmitter::INeg(const U32U64& value) {
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switch (value.Type()) {
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case Type::U32:
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@ -209,6 +209,7 @@ public:
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[[nodiscard]] U32U64 IAdd(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32 IMul(const U32& a, const U32& b);
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[[nodiscard]] U32 IDiv(const U32& a, const U32& b, bool is_signed = false);
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[[nodiscard]] U32U64 INeg(const U32U64& value);
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[[nodiscard]] U32 IAbs(const U32& value);
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[[nodiscard]] U32U64 ShiftLeftLogical(const U32U64& base, const U32& shift);
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@ -287,6 +287,8 @@ OPCODE(IAdd64, U64, U64,
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OPCODE(ISub32, U32, U32, U32, )
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OPCODE(ISub64, U64, U64, U64, )
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OPCODE(IMul32, U32, U32, U32, )
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OPCODE(SDiv32, U32, U32, U32, )
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OPCODE(UDiv32, U32, U32, U32, )
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OPCODE(INeg32, U32, U32, )
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OPCODE(INeg64, U64, U64, )
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OPCODE(IAbs32, U32, U32, )
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