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shader: Implement LOP and LOP3
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382cba94ed
commit
980cafdc27
@ -86,6 +86,8 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/integer_short_multiply_add.cpp
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frontend/maxwell/translate/impl/load_store_attribute.cpp
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frontend/maxwell/translate/impl/load_store_memory.cpp
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frontend/maxwell/translate/impl/logic_operation.cpp
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frontend/maxwell/translate/impl/logic_operation_three_input.cpp
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frontend/maxwell/translate/impl/move_predicate_to_register.cpp
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frontend/maxwell/translate/impl/move_register.cpp
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frontend/maxwell/translate/impl/move_special_register.cpp
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@ -178,8 +178,8 @@ INST(LOP_reg, "LOP (reg)", "0101 1100 0100 0---")
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INST(LOP_cbuf, "LOP (cbuf)", "0100 1100 0100 0---")
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INST(LOP_imm, "LOP (imm)", "0011 100- 0100 0---")
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INST(LOP3_reg, "LOP3 (reg)", "0101 1011 1110 0---")
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INST(LOP3_cbuf, "LOP3 (cbuf)", "0011 11-- ---- ----")
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INST(LOP3_imm, "LOP3 (imm)", "0000 001- ---- ----")
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INST(LOP3_cbuf, "LOP3 (cbuf)", "0000 001- ---- ----")
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INST(LOP3_imm, "LOP3 (imm)", "0011 11-- ---- ----")
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INST(LOP32I, "LOP32I", "0000 01-- ---- ----")
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INST(MEMBAR, "MEMBAR", "1110 1111 1001 1---")
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INST(MOV_reg, "MOV (reg)", "0101 1100 1001 1---")
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@ -5,9 +5,8 @@
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
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namespace Shader::Maxwell {
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[[nodiscard]] IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1,
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const IR::U32& operand_2, CompareOp compare_op,
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bool is_signed) {
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IR::U1 IntegerCompare(IR::IREmitter& ir, const IR::U32& operand_1, const IR::U32& operand_2,
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CompareOp compare_op, bool is_signed) {
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switch (compare_op) {
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case CompareOp::False:
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return ir.Imm1(false);
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@ -30,8 +29,8 @@ namespace Shader::Maxwell {
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}
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}
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[[nodiscard]] IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1,
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const IR::U1& predicate_2, BooleanOp bop) {
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IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1, const IR::U1& predicate_2,
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BooleanOp bop) {
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switch (bop) {
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case BooleanOp::AND:
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return ir.LogicalAnd(predicate_1, predicate_2);
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@ -43,4 +42,20 @@ namespace Shader::Maxwell {
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throw NotImplementedException("Invalid bop {}", bop);
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}
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}
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IR::U1 PredicateOperation(IR::IREmitter& ir, const IR::U32& result, PredicateOp op) {
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switch (op) {
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case PredicateOp::False:
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return ir.Imm1(false);
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case PredicateOp::True:
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return ir.Imm1(true);
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case PredicateOp::Zero:
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return ir.IEqual(result, ir.Imm32(0));
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case PredicateOp::NonZero:
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return ir.INotEqual(result, ir.Imm32(0));
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default:
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throw NotImplementedException("Invalid Predicate operation {}", op);
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}
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}
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} // namespace Shader::Maxwell
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@ -13,4 +13,6 @@ namespace Shader::Maxwell {
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[[nodiscard]] IR::U1 PredicateCombine(IR::IREmitter& ir, const IR::U1& predicate_1,
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const IR::U1& predicate_2, BooleanOp bop);
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[[nodiscard]] IR::U1 PredicateOperation(IR::IREmitter& ir, const IR::U32& result, PredicateOp op);
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} // namespace Shader::Maxwell
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@ -28,6 +28,13 @@ enum class BooleanOp : u64 {
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XOR,
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};
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enum class PredicateOp : u64 {
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False,
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True,
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Zero,
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NonZero,
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};
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class TranslatorVisitor {
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public:
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explicit TranslatorVisitor(Environment& env_, IR::Block& block) : env{env_}, ir(block) {}
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@ -0,0 +1,77 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class LogicalOp : u64 {
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AND,
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OR,
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XOR,
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PASS_B,
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};
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[[nodiscard]] IR::U32 LogicalOperation(IR::IREmitter& ir, const IR::U32& operand_1,
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const IR::U32& operand_2, LogicalOp op) {
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switch (op) {
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case LogicalOp::AND:
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return ir.BitwiseAnd(operand_1, operand_2);
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case LogicalOp::OR:
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return ir.BitwiseOr(operand_1, operand_2);
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case LogicalOp::XOR:
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return ir.BitwiseXor(operand_1, operand_2);
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case LogicalOp::PASS_B:
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return operand_2;
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default:
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throw NotImplementedException("Invalid Logical operation {}", op);
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}
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}
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void LOP(TranslatorVisitor& v, u64 insn, IR::U32 op_b) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_reg;
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BitField<39, 1, u64> neg_a;
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BitField<40, 1, u64> neg_b;
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BitField<41, 2, LogicalOp> bit_op;
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BitField<43, 1, u64> x;
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BitField<44, 2, PredicateOp> pred_op;
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BitField<48, 3, IR::Pred> pred;
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} const lop{insn};
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if (lop.x != 0) {
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throw NotImplementedException("LOP X");
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}
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IR::U32 op_a{v.X(lop.src_reg)};
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if (lop.neg_a != 0) {
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op_a = v.ir.BitwiseNot(op_a);
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}
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if (lop.neg_b != 0) {
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op_b = v.ir.BitwiseNot(op_b);
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}
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const IR::U32 result{LogicalOperation(v.ir, op_a, op_b, lop.bit_op)};
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const IR::U1 pred_result{PredicateOperation(v.ir, result, lop.pred_op)};
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v.X(lop.dest_reg, result);
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v.ir.SetPred(lop.pred, pred_result);
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}
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} // Anonymous namespace
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void TranslatorVisitor::LOP_reg(u64 insn) {
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LOP(*this, insn, GetReg20(insn));
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}
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void TranslatorVisitor::LOP_cbuf(u64 insn) {
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LOP(*this, insn, GetCbuf(insn));
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}
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void TranslatorVisitor::LOP_imm(u64 insn) {
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LOP(*this, insn, GetImm20(insn));
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}
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} // namespace Shader::Maxwell
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@ -0,0 +1,117 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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// https://forums.developer.nvidia.com/t/reverse-lut-for-lop3-lut/110651
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// Emulate GPU's LOP3.LUT (three-input logic op with 8-bit truth table)
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IR::U32 ApplyLUT(IR::IREmitter& ir, const IR::U32& a, const IR::U32& b, const IR::U32& c,
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u64 ttbl) {
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IR::U32 r{ir.Imm32(0)};
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const IR::U32 not_a{ir.BitwiseNot(a)};
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const IR::U32 not_b{ir.BitwiseNot(b)};
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const IR::U32 not_c{ir.BitwiseNot(c)};
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if (ttbl & 0x01) {
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// r |= ~a & ~b & ~c;
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const auto lhs{ir.BitwiseAnd(not_a, not_b)};
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const auto rhs{ir.BitwiseAnd(lhs, not_c)};
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r = ir.BitwiseOr(r, rhs);
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}
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if (ttbl & 0x02) {
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// r |= ~a & ~b & c;
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const auto lhs{ir.BitwiseAnd(not_a, not_b)};
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const auto rhs{ir.BitwiseAnd(lhs, c)};
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r = ir.BitwiseOr(r, rhs);
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}
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if (ttbl & 0x04) {
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// r |= ~a & b & ~c;
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const auto lhs{ir.BitwiseAnd(not_a, b)};
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const auto rhs{ir.BitwiseAnd(lhs, not_c)};
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r = ir.BitwiseOr(r, rhs);
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}
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if (ttbl & 0x08) {
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// r |= ~a & b & c;
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const auto lhs{ir.BitwiseAnd(not_a, b)};
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const auto rhs{ir.BitwiseAnd(lhs, c)};
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r = ir.BitwiseOr(r, rhs);
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}
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if (ttbl & 0x10) {
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// r |= a & ~b & ~c;
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const auto lhs{ir.BitwiseAnd(a, not_b)};
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const auto rhs{ir.BitwiseAnd(lhs, not_c)};
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r = ir.BitwiseOr(r, rhs);
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}
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if (ttbl & 0x20) {
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// r |= a & ~b & c;
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const auto lhs{ir.BitwiseAnd(a, not_b)};
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const auto rhs{ir.BitwiseAnd(lhs, c)};
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r = ir.BitwiseOr(r, rhs);
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}
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if (ttbl & 0x40) {
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// r |= a & b & ~c;
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const auto lhs{ir.BitwiseAnd(a, b)};
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const auto rhs{ir.BitwiseAnd(lhs, not_c)};
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r = ir.BitwiseOr(r, rhs);
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}
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if (ttbl & 0x80) {
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// r |= a & b & c;
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const auto lhs{ir.BitwiseAnd(a, b)};
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const auto rhs{ir.BitwiseAnd(lhs, c)};
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r = ir.BitwiseOr(r, rhs);
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}
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return r;
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}
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IR::U32 LOP3(TranslatorVisitor& v, u64 insn, const IR::U32& op_b, const IR::U32& op_c, u64 lut) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_reg;
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} const lop3{insn};
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const IR::U32 op_a{v.X(lop3.src_reg)};
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const IR::U32 result{ApplyLUT(v.ir, op_a, op_b, op_c, lut)};
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v.X(lop3.dest_reg, result);
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return result;
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}
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u64 GetLut48(u64 insn) {
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union {
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u64 raw;
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BitField<48, 8, u64> lut;
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} const lut{insn};
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return lut.lut;
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}
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} // Anonymous namespace
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void TranslatorVisitor::LOP3_reg(u64 insn) {
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union {
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u64 insn;
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BitField<28, 8, u64> lut;
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BitField<38, 1, u64> x;
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BitField<36, 2, PredicateOp> pred_op;
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BitField<48, 3, IR::Pred> pred;
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} const lop3{insn};
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if (lop3.x != 0) {
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throw NotImplementedException("LOP3 X");
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}
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const IR::U32 result{LOP3(*this, insn, GetReg20(insn), GetReg39(insn), lop3.lut)};
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const IR::U1 pred_result{PredicateOperation(ir, result, lop3.pred_op)};
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ir.SetPred(lop3.pred, pred_result);
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}
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void TranslatorVisitor::LOP3_cbuf(u64 insn) {
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LOP3(*this, insn, GetCbuf(insn), GetReg39(insn), GetLut48(insn));
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}
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void TranslatorVisitor::LOP3_imm(u64 insn) {
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LOP3(*this, insn, GetImm20(insn), GetReg39(insn), GetLut48(insn));
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}
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} // namespace Shader::Maxwell
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@ -493,30 +493,6 @@ void TranslatorVisitor::LONGJMP(u64) {
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ThrowNotImplemented(Opcode::LONGJMP);
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}
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void TranslatorVisitor::LOP_reg(u64) {
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ThrowNotImplemented(Opcode::LOP_reg);
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}
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void TranslatorVisitor::LOP_cbuf(u64) {
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ThrowNotImplemented(Opcode::LOP_cbuf);
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}
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void TranslatorVisitor::LOP_imm(u64) {
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ThrowNotImplemented(Opcode::LOP_imm);
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}
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void TranslatorVisitor::LOP3_reg(u64) {
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ThrowNotImplemented(Opcode::LOP3_reg);
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}
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void TranslatorVisitor::LOP3_cbuf(u64) {
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ThrowNotImplemented(Opcode::LOP3_cbuf);
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}
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void TranslatorVisitor::LOP3_imm(u64) {
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ThrowNotImplemented(Opcode::LOP3_imm);
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}
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void TranslatorVisitor::LOP32I(u64) {
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ThrowNotImplemented(Opcode::LOP32I);
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}
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