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shader_decode: Implement LOP3
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@ -11,6 +11,7 @@ namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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@ -79,6 +80,24 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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instr.alu.lop.pred_result_mode, instr.alu.lop.pred48);
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break;
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}
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case OpCode::Id::LOP3_C:
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case OpCode::Id::LOP3_R:
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case OpCode::Id::LOP3_IMM: {
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in LOP3 is not implemented");
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const Node op_c = GetRegister(instr.gpr39);
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const Node lut = [&]() {
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if (opcode->get().GetId() == OpCode::Id::LOP3_R) {
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return Immediate(instr.alu.lop3.GetImmLut28());
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} else {
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return Immediate(instr.alu.lop3.GetImmLut48());
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}
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}();
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WriteLop3Instruction(bb, instr.gpr0, op_a, op_b, op_c, lut);
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break;
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}
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case OpCode::Id::IMNMX_C:
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case OpCode::Id::IMNMX_R:
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case OpCode::Id::IMNMX_IMM: {
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@ -102,4 +121,45 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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return pc;
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}
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void ShaderIR::WriteLop3Instruction(BasicBlock& bb, Register dest, Node op_a, Node op_b, Node op_c,
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Node imm_lut) {
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constexpr u32 lop_iterations = 32;
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const Node one = Immediate(1);
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const Node two = Immediate(2);
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Node value{};
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for (u32 i = 0; i < lop_iterations; ++i) {
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const Node shift_amount = Immediate(i);
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const Node a = Operation(OperationCode::ILogicalShiftRight, NO_PRECISE, op_c, shift_amount);
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const Node pack_0 = Operation(OperationCode::IBitwiseAnd, NO_PRECISE, a, one);
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const Node b = Operation(OperationCode::ILogicalShiftRight, NO_PRECISE, op_b, shift_amount);
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const Node c = Operation(OperationCode::IBitwiseAnd, NO_PRECISE, b, one);
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const Node pack_1 = Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, c, one);
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const Node d = Operation(OperationCode::ILogicalShiftRight, NO_PRECISE, op_a, shift_amount);
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const Node e = Operation(OperationCode::IBitwiseAnd, NO_PRECISE, d, one);
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const Node pack_2 = Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, e, two);
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const Node pack_01 = Operation(OperationCode::IBitwiseAnd, NO_PRECISE, pack_0, pack_1);
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const Node pack_012 = Operation(OperationCode::IBitwiseAnd, NO_PRECISE, pack_01, pack_2);
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const Node shifted_bit =
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Operation(OperationCode::ILogicalShiftRight, NO_PRECISE, imm_lut, pack_012);
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const Node bit = Operation(OperationCode::IBitwiseAnd, NO_PRECISE, shifted_bit, one);
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const Node right =
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Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, bit, shift_amount);
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if (i > 0) {
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value = Operation(OperationCode::IBitwiseOr, NO_PRECISE, value, right);
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} else {
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value = right;
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}
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}
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SetRegister(bb, dest, value);
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}
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} // namespace VideoCommon::Shader
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@ -701,6 +701,8 @@ private:
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Tegra::Shader::LogicOperation logic_op, Node op_a, Node op_b,
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Tegra::Shader::PredicateResultMode predicate_mode,
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Tegra::Shader::Pred predicate);
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void WriteLop3Instruction(BasicBlock& bb, Tegra::Shader::Register dest, Node op_a, Node op_b,
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Node op_c, Node imm_lut);
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template <typename... T>
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inline Node Operation(OperationCode code, const T*... operands) {
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