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https://github.com/yuzu-emu/yuzu.git
synced 2024-08-23 08:10:40 +02:00
commit
a4b1e8ce52
@ -36,9 +36,8 @@ ARM_DynCom::ARM_DynCom() {
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state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext
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state->Emulate = 3;
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state->pc = state->Reg[15] = 0x00000000;
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state->Reg[15] = 0x00000000;
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state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
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state->servaddr = 0xFFFF0000;
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state->NirqSig = HIGH;
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VFPInit(state.get()); // Initialize the VFP
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@ -50,7 +49,7 @@ ARM_DynCom::~ARM_DynCom() {
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}
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void ARM_DynCom::SetPC(u32 pc) {
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state->pc = state->Reg[15] = pc;
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state->Reg[15] = pc;
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}
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u32 ARM_DynCom::GetPC() const {
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@ -106,7 +105,6 @@ void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
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ctx.fpscr = state->VFP[1];
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ctx.fpexc = state->VFP[2];
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ctx.reg_15 = state->Reg[15];
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ctx.mode = state->NextInstr;
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}
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@ -116,13 +114,12 @@ void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
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state->Reg[13] = ctx.sp;
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state->Reg[14] = ctx.lr;
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state->pc = ctx.pc;
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state->Reg[15] = ctx.pc;
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state->Cpsr = ctx.cpsr;
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state->VFP[1] = ctx.fpscr;
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state->VFP[2] = ctx.fpexc;
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state->Reg[15] = ctx.reg_15;
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state->NextInstr = ctx.mode;
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}
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@ -95,12 +95,6 @@ ARMul_State* ARMul_NewState(ARMul_State* state)
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state->lateabtSig = HIGH;
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state->bigendSig = LOW;
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//chy:2003-08-19
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state->CP14R0_CCD = -1;
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memset(&state->exclusive_tag_array[0], 0xFF, sizeof(state->exclusive_tag_array[0]) * 128);
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state->exclusive_access_state = 0;
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return state;
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}
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@ -118,15 +112,15 @@ void ARMul_SelectProcessor(ARMul_State* state, unsigned properties)
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state->data32Sig = HIGH;
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}
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state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW;
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state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW;
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state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW;
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state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW;
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state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW;
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state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW;
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state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW;
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state->is_pxa27x = (properties & ARM_PXA27X_Prop) ? HIGH : LOW;
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state->is_v7 = (properties & ARM_v7_Prop) ? HIGH : LOW;
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state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) != 0;
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state->is_v5 = (properties & ARM_v5_Prop) != 0;
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state->is_v5e = (properties & ARM_v5e_Prop) != 0;
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state->is_XScale = (properties & ARM_XScale_Prop) != 0;
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state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) != 0;
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state->is_v6 = (properties & ARM_v6_Prop) != 0;
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state->is_ep9312 = (properties & ARM_ep9312_Prop) != 0;
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state->is_pxa27x = (properties & ARM_PXA27X_Prop) != 0;
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state->is_v7 = (properties & ARM_v7_Prop) != 0;
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/* Only initialse the coprocessor support once we
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know what kind of chip we are dealing with. */
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@ -164,9 +158,4 @@ void ARMul_Reset(ARMul_State* state)
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state->AbortAddr = 1;
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state->NumInstrs = 0;
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state->NumNcycles = 0;
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state->NumScycles = 0;
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state->NumIcycles = 0;
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state->NumCcycles = 0;
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state->NumFcycles = 0;
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}
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@ -74,88 +74,69 @@ typedef unsigned ARMul_CPWrites(ARMul_State* state, unsigned reg, ARMword value)
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#define VFP_REG_NUM 64
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struct ARMul_State
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{
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ARMword Emulate; /* to start and stop emulation */
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unsigned EndCondition; /* reason for stopping */
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unsigned ErrorCode; /* type of illegal instruction */
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ARMword Emulate; // To start and stop emulation
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unsigned EndCondition; // Reason for stopping
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unsigned ErrorCode; // Type of illegal instruction
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/* Order of the following register should not be modified */
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ARMword Reg[16]; /* the current register file */
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ARMword Cpsr; /* the current psr */
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// Order of the following register should not be modified
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ARMword Reg[16]; // The current register file
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ARMword Cpsr; // The current PSR
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ARMword Spsr_copy;
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ARMword phys_pc;
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ARMword Reg_usr[2];
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ARMword Reg_svc[2]; /* R13_SVC R14_SVC */
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ARMword Reg_abort[2]; /* R13_ABORT R14_ABORT */
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ARMword Reg_undef[2]; /* R13 UNDEF R14 UNDEF */
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ARMword Reg_irq[2]; /* R13_IRQ R14_IRQ */
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ARMword Reg_firq[7]; /* R8---R14 FIRQ */
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ARMword Spsr[7]; /* the exception psr's */
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ARMword Mode; /* the current mode */
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ARMword Bank; /* the current register bank */
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ARMword exclusive_tag; /* the address for which the local monitor is in exclusive access mode */
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ARMword Reg_svc[2]; // R13_SVC R14_SVC
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ARMword Reg_abort[2]; // R13_ABORT R14_ABORT
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ARMword Reg_undef[2]; // R13 UNDEF R14 UNDEF
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ARMword Reg_irq[2]; // R13_IRQ R14_IRQ
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ARMword Reg_firq[7]; // R8---R14 FIRQ
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ARMword Spsr[7]; // The exception psr's
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ARMword Mode; // The current mode
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ARMword Bank; // The current register bank
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ARMword exclusive_tag; // The address for which the local monitor is in exclusive access mode
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ARMword exclusive_state;
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ARMword exclusive_result;
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ARMword CP15[VFP_BASE - CP15_BASE];
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ARMword VFP[3]; /* FPSID, FPSCR, and FPEXC */
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/* VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
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VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
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and only 32 singleword registers are accessible (S0-S31). */
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ARMword VFP[3]; // FPSID, FPSCR, and FPEXC
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// VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
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// VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
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// and only 32 singleword registers are accessible (S0-S31).
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ARMword ExtReg[VFP_REG_NUM];
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/* ---- End of the ordered registers ---- */
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ARMword RegBank[7][16]; /* all the registers */
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//chy:2003-08-19, used in arm xscale
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/* 40 bit accumulator. We always keep this 64 bits wide,
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and move only 40 bits out of it in an MRA insn. */
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ARMdword Accumulator;
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ARMword RegBank[7][16]; // all the registers
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ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
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unsigned long long int icounter, debug_icounter, kernel_icounter;
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ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed
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unsigned int shifter_carry_out;
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/* add armv6 flags dyf:2010-08-09 */
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// Add armv6 flags dyf:2010-08-09
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ARMword GEFlag, EFlag, AFlag, QFlag;
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//chy:2003-08-19, used in arm v5e|xscale
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ARMword SFlag;
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#ifdef MODET
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ARMword TFlag; /* Thumb state */
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ARMword TFlag; // Thumb state
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#endif
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ARMword instr, pc, temp; /* saved register state */
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ARMword loaded, decoded; /* saved pipeline state */
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//chy 2006-04-12 for ICE breakpoint
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ARMword loaded_addr, decoded_addr; /* saved pipeline state addr*/
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unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
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unsigned long long NumInstrs; /* the number of instructions executed */
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unsigned long long NumInstrs; // The number of instructions executed
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unsigned NumInstrsToExecute;
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ARMword currentexaddr;
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ARMword currentexval;
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ARMword currentexvald;
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ARMword servaddr;
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unsigned NextInstr;
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unsigned VectorCatch; /* caught exception mask */
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unsigned CallDebug; /* set to call the debugger */
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unsigned CanWatch; /* set by memory interface if its willing to suffer the
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overhead of checking for watchpoints on each memory
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access */
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unsigned VectorCatch; // Caught exception mask
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ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */
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ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */
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ARMul_LDCs *LDC[16]; /* LDC instruction */
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ARMul_STCs *STC[16]; /* STC instruction */
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ARMul_MRCs *MRC[16]; /* MRC instruction */
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ARMul_MCRs *MCR[16]; /* MCR instruction */
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ARMul_MRRCs *MRRC[16]; /* MRRC instruction */
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ARMul_MCRRs *MCRR[16]; /* MCRR instruction */
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ARMul_CDPs *CDP[16]; /* CDP instruction */
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ARMul_CPReads *CPRead[16]; /* Read CP register */
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ARMul_CPWrites *CPWrite[16]; /* Write CP register */
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unsigned char *CPData[16]; /* Coprocessor data */
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unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
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ARMul_CPInits* CPInit[16]; // Coprocessor initialisers
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ARMul_CPExits* CPExit[16]; // Coprocessor finalisers
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ARMul_LDCs* LDC[16]; // LDC instruction
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ARMul_STCs* STC[16]; // STC instruction
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ARMul_MRCs* MRC[16]; // MRC instruction
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ARMul_MCRs* MCR[16]; // MCR instruction
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ARMul_MRRCs* MRRC[16]; // MRRC instruction
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ARMul_MCRRs* MCRR[16]; // MCRR instruction
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ARMul_CDPs* CDP[16]; // CDP instruction
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ARMul_CPReads* CPRead[16]; // Read CP register
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ARMul_CPWrites* CPWrite[16]; // Write CP register
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unsigned char* CPData[16]; // Coprocessor data
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unsigned char const* CPRegWords[16]; // Map of coprocessor register sizes
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unsigned Debug; /* show instructions as they are executed */
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unsigned NresetSig; /* reset the processor */
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unsigned Debug; // Show instructions as they are executed
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unsigned NresetSig; // Reset the processor
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unsigned NfiqSig;
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unsigned NirqSig;
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@ -199,54 +180,34 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
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*/
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unsigned lateabtSig;
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ARMword Vector; /* synthesize aborts in cycle modes */
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ARMword Aborted; /* sticky flag for aborts */
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ARMword Reseted; /* sticky flag for Reset */
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ARMword Inted, LastInted; /* sticky flags for interrupts */
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ARMword Base; /* extra hand for base writeback */
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ARMword AbortAddr; /* to keep track of Prefetch aborts */
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ARMword Vector; // Synthesize aborts in cycle modes
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ARMword Aborted; // Sticky flag for aborts
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ARMword Reseted; // Sticky flag for Reset
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ARMword Inted, LastInted; // Sticky flags for interrupts
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ARMword Base; // Extra hand for base writeback
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ARMword AbortAddr; // To keep track of Prefetch aborts
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int verbose; /* non-zero means print various messages like the banner */
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// For differentiating ARM core emulaiton.
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bool is_v4; // Are we emulating a v4 architecture (or higher)?
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bool is_v5; // Are we emulating a v5 architecture?
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bool is_v5e; // Are we emulating a v5e architecture?
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bool is_v6; // Are we emulating a v6 architecture?
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bool is_v7; // Are we emulating a v7 architecture?
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bool is_XScale; // Are we emulating an XScale architecture?
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bool is_iWMMXt; // Are we emulating an iWMMXt co-processor?
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bool is_ep9312; // Are we emulating a Cirrus Maverick co-processor?
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bool is_pxa27x; // Are we emulating a Intel PXA27x co-processor?
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int mmu_inited;
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// ARM_ARM A2-18
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// 0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
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int abort_model;
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//chy: 2003-08-11, for different arm core type
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unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
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unsigned is_v5; /* Are we emulating a v5 architecture ? */
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unsigned is_v5e; /* Are we emulating a v5e architecture ? */
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unsigned is_v6; /* Are we emulating a v6 architecture ? */
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unsigned is_v7; /* Are we emulating a v7 architecture ? */
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unsigned is_XScale; /* Are we emulating an XScale architecture ? */
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unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
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unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
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unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */
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//chy: seems only used in xscale's CP14
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ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */
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//teawater add for arm2x86 2005.07.05-------------------------------------------
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//arm_arm A2-18
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int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
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/*added by ksh in 2005-10-1*/
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cpu_config_t *cpu;
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/* added LPC remap function */
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int vector_remap_flag;
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u32 vector_remap_addr;
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u32 vector_remap_size;
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u32 step;
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u32 cycle;
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/* monitored memory for exclusice access */
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ARMword exclusive_tag_array[128];
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/* 1 means exclusive access and 0 means open access */
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ARMword exclusive_access_state;
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// Added by ksh in 2005-10-1
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cpu_config_t* cpu;
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u32 CurrInstr;
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u32 last_pc; /* the last pc executed */
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u32 last_instr; /* the last inst executed */
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u32 last_pc; // The last PC executed
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u32 last_instr; // The last instruction executed
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u32 WriteAddr[17];
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u32 WriteData[17];
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u32 WritePc[17];
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@ -23,7 +23,6 @@ struct ThreadContext {
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u32 fpexc;
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// These are not part of native ThreadContext, but needed by emu
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u32 reg_15;
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u32 mode;
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};
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@ -50,7 +50,7 @@ static void ResetThread(Thread* t, u32 arg, s32 lowest_priority) {
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memset(&t->context, 0, sizeof(Core::ThreadContext));
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t->context.cpu_registers[0] = arg;
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t->context.pc = t->context.reg_15 = t->entry_point;
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t->context.pc = t->entry_point;
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t->context.sp = t->stack_top;
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t->context.cpsr = 0x1F; // Usermode
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