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https://github.com/yuzu-emu/yuzu.git
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shader: Implement F2F
This commit is contained in:
parent
8b3b9c3371
commit
a62f04efab
@ -72,6 +72,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/floating_point_add.cpp
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frontend/maxwell/translate/impl/floating_point_compare.cpp
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frontend/maxwell/translate/impl/floating_point_compare_and_set.cpp
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frontend/maxwell/translate/impl/floating_point_conversion_floating_point.cpp
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frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
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frontend/maxwell/translate/impl/floating_point_fused_multiply_add.cpp
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frontend/maxwell/translate/impl/floating_point_min_max.cpp
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@ -1361,7 +1361,7 @@ U32U64 IREmitter::UConvert(size_t result_bitsize, const U32U64& value) {
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throw NotImplementedException("Conversion from {} to {} bits", value.Type(), result_bitsize);
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}
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F16F32F64 IREmitter::FPConvert(size_t result_bitsize, const F16F32F64& value) {
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F16F32F64 IREmitter::FPConvert(size_t result_bitsize, const F16F32F64& value, FpControl control) {
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switch (result_bitsize) {
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case 16:
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switch (value.Type()) {
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@ -1369,7 +1369,7 @@ F16F32F64 IREmitter::FPConvert(size_t result_bitsize, const F16F32F64& value) {
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// Nothing to do
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return value;
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case Type::F32:
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return Inst<F16>(Opcode::ConvertF16F32, value);
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return Inst<F16>(Opcode::ConvertF16F32, Flags{control}, value);
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case Type::F64:
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throw LogicError("Illegal conversion from F64 to F16");
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default:
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@ -1379,12 +1379,12 @@ F16F32F64 IREmitter::FPConvert(size_t result_bitsize, const F16F32F64& value) {
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case 32:
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switch (value.Type()) {
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case Type::F16:
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return Inst<F32>(Opcode::ConvertF32F16, value);
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return Inst<F32>(Opcode::ConvertF32F16, Flags{control}, value);
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case Type::F32:
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// Nothing to do
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return value;
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case Type::F64:
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return Inst<F64>(Opcode::ConvertF32F64, value);
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return Inst<F32>(Opcode::ConvertF32F64, Flags{control}, value);
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default:
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break;
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}
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@ -1394,10 +1394,10 @@ F16F32F64 IREmitter::FPConvert(size_t result_bitsize, const F16F32F64& value) {
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case Type::F16:
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throw LogicError("Illegal conversion from F16 to F64");
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case Type::F32:
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return Inst<F64>(Opcode::ConvertF64F32, Flags{control}, value);
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case Type::F64:
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// Nothing to do
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return value;
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case Type::F64:
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return Inst<F64>(Opcode::ConvertF32F64, value);
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default:
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break;
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}
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@ -216,7 +216,8 @@ public:
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const Value& value);
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[[nodiscard]] U32U64 UConvert(size_t result_bitsize, const U32U64& value);
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[[nodiscard]] F16F32F64 FPConvert(size_t result_bitsize, const F16F32F64& value);
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[[nodiscard]] F16F32F64 FPConvert(size_t result_bitsize, const F16F32F64& value,
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FpControl control = {});
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[[nodiscard]] Value ImageSampleImplicitLod(const Value& handle, const Value& coords,
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const F32& bias, const Value& offset,
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@ -0,0 +1,180 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_encoding.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_helper.h"
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namespace Shader::Maxwell {
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namespace {
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enum class FloatFormat : u64 {
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F16 = 1,
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F32 = 2,
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F64 = 3,
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};
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enum class RoundingOp : u64 {
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None = 0,
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Pass = 3,
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Round = 8,
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Floor = 9,
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Ceil = 10,
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Trunc = 11,
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};
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[[nodiscard]] u32 WidthSize(FloatFormat width) {
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switch (width) {
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case FloatFormat::F16:
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return 16;
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case FloatFormat::F32:
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return 32;
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case FloatFormat::F64:
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return 64;
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default:
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throw NotImplementedException("Invalid width {}", width);
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}
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}
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void F2F(TranslatorVisitor& v, u64 insn, const IR::F16F32F64& src_a, bool abs) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<44, 1, u64> ftz;
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BitField<45, 1, u64> neg;
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BitField<50, 1, u64> sat;
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BitField<39, 4, u64> rounding_op;
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BitField<39, 2, FpRounding> rounding;
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BitField<10, 2, FloatFormat> src_size;
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BitField<8, 2, FloatFormat> dst_size;
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[[nodiscard]] RoundingOp RoundingOperation() const {
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constexpr u64 rounding_mask = 0x0B;
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return static_cast<RoundingOp>(rounding_op.Value() & rounding_mask);
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}
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} const f2f{insn};
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IR::F16F32F64 input{v.ir.FPAbsNeg(src_a, abs, f2f.neg != 0)};
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const bool any_fp64{f2f.src_size == FloatFormat::F64 || f2f.dst_size == FloatFormat::F64};
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IR::FpControl fp_control{
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.no_contraction{false},
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.rounding{IR::FpRounding::DontCare},
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.fmz_mode{f2f.ftz != 0 && !any_fp64 ? IR::FmzMode::FTZ : IR::FmzMode::None},
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};
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if (f2f.src_size != f2f.dst_size) {
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fp_control.rounding = CastFpRounding(f2f.rounding);
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input = v.ir.FPConvert(WidthSize(f2f.dst_size), input, fp_control);
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} else {
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switch (f2f.RoundingOperation()) {
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case RoundingOp::None:
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case RoundingOp::Pass:
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// Make sure NANs are handled properly
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switch (f2f.src_size) {
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case FloatFormat::F16:
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input = v.ir.FPAdd(input, v.ir.FPConvert(16, v.ir.Imm32(0.0f)), fp_control);
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break;
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case FloatFormat::F32:
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input = v.ir.FPAdd(input, v.ir.Imm32(0.0f), fp_control);
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break;
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case FloatFormat::F64:
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input = v.ir.FPAdd(input, v.ir.Imm64(0.0), fp_control);
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break;
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}
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break;
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case RoundingOp::Round:
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input = v.ir.FPRoundEven(input, fp_control);
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break;
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case RoundingOp::Floor:
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input = v.ir.FPFloor(input, fp_control);
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break;
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case RoundingOp::Ceil:
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input = v.ir.FPCeil(input, fp_control);
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break;
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case RoundingOp::Trunc:
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input = v.ir.FPTrunc(input, fp_control);
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break;
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default:
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throw NotImplementedException("Unimplemented rounding mode {}", f2f.rounding.Value());
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}
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}
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if (f2f.sat != 0 && !any_fp64) {
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input = v.ir.FPSaturate(input);
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}
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switch (f2f.dst_size) {
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case FloatFormat::F16: {
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const IR::F16 imm{v.ir.FPConvert(16, v.ir.Imm32(0.0f))};
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v.X(f2f.dest_reg, v.ir.PackFloat2x16(v.ir.CompositeConstruct(input, imm)));
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break;
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}
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case FloatFormat::F32:
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v.F(f2f.dest_reg, input);
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break;
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case FloatFormat::F64:
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v.D(f2f.dest_reg, input);
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break;
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default:
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throw NotImplementedException("Invalid dest format {}", f2f.dst_size.Value());
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}
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}
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} // Anonymous namespace
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void TranslatorVisitor::F2F_reg(u64 insn) {
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union {
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u64 insn;
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BitField<49, 1, u64> abs;
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BitField<10, 2, FloatFormat> src_size;
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BitField<41, 1, u64> selector;
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} const f2f{insn};
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IR::F16F32F64 src_a;
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switch (f2f.src_size) {
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case FloatFormat::F16: {
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auto [lhs_a, rhs_a]{Extract(ir, GetReg20(insn), Swizzle::H1_H0)};
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src_a = f2f.selector != 0 ? rhs_a : lhs_a;
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break;
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}
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case FloatFormat::F32:
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src_a = GetFloatReg20(insn);
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break;
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case FloatFormat::F64:
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src_a = GetDoubleReg20(insn);
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break;
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default:
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throw NotImplementedException("Invalid dest format {}", f2f.src_size.Value());
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}
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F2F(*this, insn, src_a, f2f.abs != 0);
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}
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void TranslatorVisitor::F2F_cbuf(u64 insn) {
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union {
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u64 insn;
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BitField<49, 1, u64> abs;
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BitField<10, 2, FloatFormat> src_size;
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BitField<41, 1, u64> selector;
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} const f2f{insn};
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IR::F16F32F64 src_a;
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switch (f2f.src_size) {
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case FloatFormat::F16: {
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auto [lhs_a, rhs_a]{Extract(ir, GetCbuf(insn), Swizzle::H1_H0)};
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src_a = f2f.selector != 0 ? rhs_a : lhs_a;
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break;
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}
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case FloatFormat::F32:
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src_a = GetFloatCbuf(insn);
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break;
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case FloatFormat::F64:
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src_a = GetDoubleCbuf(insn);
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break;
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default:
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throw NotImplementedException("Invalid dest format {}", f2f.src_size.Value());
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}
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F2F(*this, insn, src_a, f2f.abs != 0);
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}
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void TranslatorVisitor::F2F_imm([[maybe_unused]] u64 insn) {
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throw NotImplementedException("Instruction");
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}
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} // namespace Shader::Maxwell
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@ -117,18 +117,6 @@ void TranslatorVisitor::DSETP_imm(u64) {
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ThrowNotImplemented(Opcode::DSETP_imm);
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}
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void TranslatorVisitor::F2F_reg(u64) {
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ThrowNotImplemented(Opcode::F2F_reg);
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}
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void TranslatorVisitor::F2F_cbuf(u64) {
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ThrowNotImplemented(Opcode::F2F_cbuf);
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}
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void TranslatorVisitor::F2F_imm(u64) {
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ThrowNotImplemented(Opcode::F2F_imm);
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}
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void TranslatorVisitor::FCHK_reg(u64) {
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ThrowNotImplemented(Opcode::FCHK_reg);
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}
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@ -404,7 +404,9 @@ void VisitFpModifiers(Info& info, IR::Inst& inst) {
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case IR::Opcode::FPOrdLessThanEqual32:
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case IR::Opcode::FPUnordLessThanEqual32:
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case IR::Opcode::FPOrdGreaterThanEqual32:
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case IR::Opcode::FPUnordGreaterThanEqual32: {
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case IR::Opcode::FPUnordGreaterThanEqual32:
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case IR::Opcode::ConvertF16F32:
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case IR::Opcode::ConvertF64F32: {
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const auto control{inst.Flags<IR::FpControl>()};
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switch (control.fmz_mode) {
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case IR::FmzMode::DontCare:
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