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Merge pull request #929 from neobrain/geoshader_definitions
Pica/Shader: Add geometry shader definitions.
This commit is contained in:
commit
aa6dfdb827
@ -259,7 +259,7 @@ void GraphicsVertexShaderModel::OnUpdate()
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for (auto pattern : Pica::g_state.vs.swizzle_data)
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info.swizzle_info.push_back({pattern});
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info.labels.insert({ Pica::g_state.regs.vs_main_offset, "main" });
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info.labels.insert({ Pica::g_state.regs.vs.main_offset, "main" });
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endResetModel();
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}
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@ -45,7 +45,7 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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if (GPU::g_skip_frame && id != PICA_REG_INDEX(trigger_irq))
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return;
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// TODO: Figure out how register masking acts on e.g. vs_uniform_setup.set_value
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// TODO: Figure out how register masking acts on e.g. vs.uniform_setup.set_value
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u32 old_value = regs[id];
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regs[id] = (old_value & ~mask) | (value & mask);
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@ -282,7 +282,7 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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&geometry_dumper, _1, _2, _3));
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// Send to vertex shader
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VertexShader::OutputVertex output = VertexShader::RunShader(input, attribute_config.GetNumTotalAttributes());
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VertexShader::OutputVertex output = VertexShader::RunShader(input, attribute_config.GetNumTotalAttributes(), g_state.regs.vs, g_state.vs);
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if (is_indexed) {
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// TODO: Add processed vertex to vertex cache!
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@ -321,35 +321,35 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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break;
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}
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case PICA_REG_INDEX(vs_bool_uniforms):
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case PICA_REG_INDEX(vs.bool_uniforms):
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for (unsigned i = 0; i < 16; ++i)
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g_state.vs.uniforms.b[i] = (regs.vs_bool_uniforms.Value() & (1 << i)) != 0;
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g_state.vs.uniforms.b[i] = (regs.vs.bool_uniforms.Value() & (1 << i)) != 0;
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break;
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case PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[0], 0x2b1):
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case PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[1], 0x2b2):
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case PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[2], 0x2b3):
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case PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[3], 0x2b4):
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case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1):
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case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[1], 0x2b2):
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case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[2], 0x2b3):
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case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[3], 0x2b4):
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{
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int index = (id - PICA_REG_INDEX_WORKAROUND(vs_int_uniforms[0], 0x2b1));
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auto values = regs.vs_int_uniforms[index];
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int index = (id - PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1));
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auto values = regs.vs.int_uniforms[index];
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g_state.vs.uniforms.i[index] = Math::Vec4<u8>(values.x, values.y, values.z, values.w);
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LOG_TRACE(HW_GPU, "Set integer uniform %d to %02x %02x %02x %02x",
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index, values.x.Value(), values.y.Value(), values.z.Value(), values.w.Value());
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break;
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}
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[0], 0x2c1):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[1], 0x2c2):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[2], 0x2c3):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[3], 0x2c4):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[4], 0x2c5):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[5], 0x2c6):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[6], 0x2c7):
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case PICA_REG_INDEX_WORKAROUND(vs_uniform_setup.set_value[7], 0x2c8):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[0], 0x2c1):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[1], 0x2c2):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[2], 0x2c3):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[3], 0x2c4):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[4], 0x2c5):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[5], 0x2c6):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[6], 0x2c7):
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case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[7], 0x2c8):
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{
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auto& uniform_setup = regs.vs_uniform_setup;
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auto& uniform_setup = regs.vs.uniform_setup;
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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// it directly write the values?
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@ -392,32 +392,32 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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}
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// Load shader program code
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[0], 0x2cc):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[1], 0x2cd):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[2], 0x2ce):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[3], 0x2cf):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[4], 0x2d0):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[5], 0x2d1):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[6], 0x2d2):
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case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[7], 0x2d3):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[0], 0x2cc):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[1], 0x2cd):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[2], 0x2ce):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[3], 0x2cf):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[4], 0x2d0):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[5], 0x2d1):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[6], 0x2d2):
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case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[7], 0x2d3):
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{
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g_state.vs.program_code[regs.vs_program.offset] = value;
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regs.vs_program.offset++;
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g_state.vs.program_code[regs.vs.program.offset] = value;
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regs.vs.program.offset++;
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break;
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}
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// Load swizzle pattern data
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[0], 0x2d6):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[1], 0x2d7):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[2], 0x2d8):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[3], 0x2d9):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[4], 0x2da):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[5], 0x2db):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[6], 0x2dc):
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case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[7], 0x2dd):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[0], 0x2d6):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[1], 0x2d7):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[2], 0x2d8):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[3], 0x2d9):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[4], 0x2da):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[5], 0x2db):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[6], 0x2dc):
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case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[7], 0x2dd):
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{
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g_state.vs.swizzle_data[regs.vs_swizzle_patterns.offset] = value;
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regs.vs_swizzle_patterns.offset++;
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g_state.vs.swizzle_data[regs.vs.swizzle_patterns.offset] = value;
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regs.vs.swizzle_patterns.offset++;
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break;
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}
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@ -788,25 +788,27 @@ struct Regs {
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List = 0,
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Strip = 1,
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Fan = 2,
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ListIndexed = 3, // TODO: No idea if this is correct
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Shader = 3, // Programmable setup unit implemented in a geometry shader
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};
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BitField<8, 2, TriangleTopology> triangle_topology;
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INSERT_PADDING_WORDS(0x51);
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INSERT_PADDING_WORDS(0x21);
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struct ShaderConfig {
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BitField<0, 16, u32> bool_uniforms;
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BitField<0, 16, u32> vs_bool_uniforms;
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union {
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BitField< 0, 8, u32> x;
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BitField< 8, 8, u32> y;
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BitField<16, 8, u32> z;
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BitField<24, 8, u32> w;
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} vs_int_uniforms[4];
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} int_uniforms[4];
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INSERT_PADDING_WORDS(0x5);
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// Offset to shader program entry point (in words)
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BitField<0, 16, u32> vs_main_offset;
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BitField<0, 16, u32> main_offset;
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union {
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BitField< 0, 4, u64> attribute0_register;
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@ -835,8 +837,9 @@ struct Regs {
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};
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return (int)fields[attribute_index];
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}
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} vs_input_register_map;
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} input_register_map;
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// OUTMAP_MASK, 0x28E, CODETRANSFER_END
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INSERT_PADDING_WORDS(0x3);
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struct {
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@ -853,16 +856,16 @@ struct Regs {
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union {
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// Index of the next uniform to write to
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// TODO: ctrulib uses 8 bits for this, however that seems to yield lots of invalid indices
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// TODO: Maybe the uppermost index is for the geometry shader? Investigate!
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BitField<0, 7, u32> index;
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BitField<31, 1, Format> format;
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};
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// Writing to these registers sets the "current" uniform.
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// TODO: It's not clear how the hardware stores what the "current" uniform is.
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// Writing to these registers sets the current uniform.
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u32 set_value[8];
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} vs_uniform_setup;
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} uniform_setup;
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INSERT_PADDING_WORDS(0x2);
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@ -872,9 +875,8 @@ struct Regs {
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u32 offset;
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// Writing to these registers sets the "current" word in the shader program.
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// TODO: It's not clear how the hardware stores what the "current" word is.
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u32 set_word[8];
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} vs_program;
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} program;
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INSERT_PADDING_WORDS(0x1);
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@ -885,12 +887,17 @@ struct Regs {
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// Incremented with each instruction write.
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u32 offset;
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// Writing to these registers sets the "current" swizzle pattern in the table.
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// TODO: It's not clear how the hardware stores what the "current" swizzle pattern is.
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// Writing to these registers sets the current swizzle pattern in the table.
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u32 set_word[8];
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} vs_swizzle_patterns;
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} swizzle_patterns;
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INSERT_PADDING_WORDS(0x22);
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INSERT_PADDING_WORDS(0x2);
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};
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ShaderConfig gs;
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ShaderConfig vs;
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INSERT_PADDING_WORDS(0x20);
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// Map register indices to names readable by humans
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// Used for debugging purposes, so performance is not an issue here
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@ -937,13 +944,20 @@ struct Regs {
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ADD_FIELD(vs_default_attributes_setup);
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ADD_FIELD(command_buffer);
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ADD_FIELD(triangle_topology);
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ADD_FIELD(vs_bool_uniforms);
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ADD_FIELD(vs_int_uniforms);
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ADD_FIELD(vs_main_offset);
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ADD_FIELD(vs_input_register_map);
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ADD_FIELD(vs_uniform_setup);
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ADD_FIELD(vs_program);
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ADD_FIELD(vs_swizzle_patterns);
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ADD_FIELD(gs.bool_uniforms);
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ADD_FIELD(gs.int_uniforms);
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ADD_FIELD(gs.main_offset);
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ADD_FIELD(gs.input_register_map);
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ADD_FIELD(gs.uniform_setup);
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ADD_FIELD(gs.program);
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ADD_FIELD(gs.swizzle_patterns);
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ADD_FIELD(vs.bool_uniforms);
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ADD_FIELD(vs.int_uniforms);
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ADD_FIELD(vs.main_offset);
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ADD_FIELD(vs.input_register_map);
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ADD_FIELD(vs.uniform_setup);
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ADD_FIELD(vs.program);
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ADD_FIELD(vs.swizzle_patterns);
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#undef ADD_FIELD
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@ -1015,17 +1029,14 @@ ASSERT_REG_POSITION(trigger_draw_indexed, 0x22f);
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ASSERT_REG_POSITION(vs_default_attributes_setup, 0x232);
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ASSERT_REG_POSITION(command_buffer, 0x238);
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ASSERT_REG_POSITION(triangle_topology, 0x25e);
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ASSERT_REG_POSITION(vs_bool_uniforms, 0x2b0);
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ASSERT_REG_POSITION(vs_int_uniforms, 0x2b1);
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ASSERT_REG_POSITION(vs_main_offset, 0x2ba);
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ASSERT_REG_POSITION(vs_input_register_map, 0x2bb);
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ASSERT_REG_POSITION(vs_uniform_setup, 0x2c0);
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ASSERT_REG_POSITION(vs_program, 0x2cb);
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ASSERT_REG_POSITION(vs_swizzle_patterns, 0x2d5);
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ASSERT_REG_POSITION(gs, 0x280);
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ASSERT_REG_POSITION(vs, 0x2b0);
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#undef ASSERT_REG_POSITION
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#endif // !defined(_MSC_VER)
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static_assert(sizeof(Regs::ShaderConfig) == 0x30 * sizeof(u32), "ShaderConfig structure has incorrect size");
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// The total number of registers is chosen arbitrarily, but let's make sure it's not some odd value anyway.
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static_assert(sizeof(Regs) <= 0x300 * sizeof(u32), "Register set structure larger than it should be");
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static_assert(sizeof(Regs) >= 0x300 * sizeof(u32), "Register set structure smaller than it should be");
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@ -1135,7 +1146,7 @@ struct State {
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Regs regs;
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/// Vertex shader memory
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struct {
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struct ShaderSetup {
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struct {
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Math::Vec4<float24> f[96];
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std::array<bool, 16> b;
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@ -1146,7 +1157,10 @@ struct State {
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std::array<u32, 1024> program_code;
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std::array<u32, 1024> swizzle_data;
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} vs;
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};
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ShaderSetup vs;
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ShaderSetup gs;
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/// Current Pica command list
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struct {
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@ -20,8 +20,9 @@ template<typename VertexType>
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void PrimitiveAssembler<VertexType>::SubmitVertex(VertexType& vtx, TriangleHandler triangle_handler)
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{
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switch (topology) {
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// TODO: Figure out what's different with TriangleTopology::Shader.
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case Regs::TriangleTopology::List:
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case Regs::TriangleTopology::ListIndexed:
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case Regs::TriangleTopology::Shader:
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if (buffer_index < 2) {
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buffer[buffer_index++] = vtx;
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} else {
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@ -546,20 +546,18 @@ static void ProcessShaderCode(VertexShaderState& state) {
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static Common::Profiling::TimingCategory shader_category("Vertex Shader");
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OutputVertex RunShader(const InputVertex& input, int num_attributes) {
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OutputVertex RunShader(const InputVertex& input, int num_attributes, const Regs::ShaderConfig& config, const State::ShaderSetup& setup) {
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Common::Profiling::ScopeTimer timer(shader_category);
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const auto& regs = g_state.regs;
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const auto& vs = g_state.vs;
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VertexShaderState state;
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const u32* main = &vs.program_code[regs.vs_main_offset];
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const u32* main = &setup.program_code[config.main_offset];
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state.program_counter = (u32*)main;
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state.debug.max_offset = 0;
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state.debug.max_opdesc_id = 0;
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// Setup input register table
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const auto& attribute_register_map = regs.vs_input_register_map;
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const auto& attribute_register_map = config.input_register_map;
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float24 dummy_register;
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boost::fill(state.input_register_table, &dummy_register);
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@ -584,16 +582,16 @@ OutputVertex RunShader(const InputVertex& input, int num_attributes) {
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state.conditional_code[1] = false;
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ProcessShaderCode(state);
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DebugUtils::DumpShader(vs.program_code.data(), state.debug.max_offset, vs.swizzle_data.data(),
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state.debug.max_opdesc_id, regs.vs_main_offset,
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regs.vs_output_attributes);
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DebugUtils::DumpShader(setup.program_code.data(), state.debug.max_offset, setup.swizzle_data.data(),
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state.debug.max_opdesc_id, config.main_offset,
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g_state.regs.vs_output_attributes); // TODO: Don't hardcode VS here
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// Setup output data
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OutputVertex ret;
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// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
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// figure out what those circumstances are and enable the remaining outputs then.
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for (int i = 0; i < 7; ++i) {
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const auto& output_register_map = regs.vs_output_attributes[i];
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const auto& output_register_map = g_state.regs.vs_output_attributes[i]; // TODO: Don't hardcode VS here
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u32 semantics[4] = {
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output_register_map.map_x, output_register_map.map_y,
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@ -65,7 +65,7 @@ struct OutputVertex {
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static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
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static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has invalid size");
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OutputVertex RunShader(const InputVertex& input, int num_attributes);
|
||||
OutputVertex RunShader(const InputVertex& input, int num_attributes, const Regs::ShaderConfig& config, const State::ShaderSetup& setup);
|
||||
|
||||
} // namespace
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user